#FPGA 2GRVI Phalanx at Hot Chips 31: The First Kilocore RISC-V RV64I with HBM2 High Bandwidth Memory.@xilinxinc @risc_v @hotchipsorg

#FPGA The @risc_v Composable Custom Extensions Task Group will run a RISC-V Extension Logic Interface Workshop in late Jan 2025. Here is the invite, date poll, and call for presenters:. (Open to RVI members.). Related:.

#FPGA Last orders for Virtex UltraScale+ HBM

#PIM #PNP #memory_accelerators #programming_models.

#HBM

#MX

Part 1 was wonderful. Looking forward to Part 2 tomorrow. Thank you, speakers and participants. I’m told ~170 online at one point, amazing for a quick grassroots production. Well done, Guy Lemieux (UBC)!. Roughly half the talks mentioned an extension logic interface. It’s time.

I saw the pink hardhats and tie, and instantly knew what this was, no need for a photo caption. Congratulations to the @WaterlooMath community. You've come a long, long way from our wonderful brutalist Math & Computer buliding. Does any other university have FOUR math buildings?.

#FPGA Join us for a Soft @risc_v Systems Workshop!.Thu-Fri, Nov. 7-8, 08:00-12:00PST/16:00-20:00UTC. Free. Online via Zoom. All welcome. Register via:.Thanks to these speakers, it will indeed be a celebration of the vibrant RISC-V soft processor ecosystem.

RT @NickBrownHPC: Lots of interesting discussions on the #RISCVSummit keynote panel discussing #RISCV in #HPC, thanks for the invitation to….

Hello from the NA @risc_v Summit! Please say hello — ESPECIALLY if you’d like to learn more about our new Composable Custom Extensions Task Group: extending RISC-V’s leadership in custom computing, together.

RT @jangray: @ogawa_tter The paper might have referenced MS Catapult and Brainwave, the world’s biggest deployment of FPGAs as accelerators….

#FPGA and the first generation of devices (Virtex UltraScale+ HBM, Stratix 10 MX/NX) that even began to address FPGAs’ extremely uncompetitive DRAM bandwidth by providing integrated HBM2 support were quietly taken to the woodshed, end of life’d decades early, killed by AI. 🪦.

Wow! The Nov 7-8 Soft @risc_v Systems Workshop has 250 registrants. We’re extending the talk submission deadline to Oct 20 (anywhere), notifications Oct 21. Workshop: Register: Propose a talk: All welcome.

Wow! The Nov 7-8 Soft @risc_v Systems Workshop has 250 registrants. We’re extending the talk submission deadline to Oct 20 (anywhere), notifications Oct 21. Workshop: Register: Propose a talk:. All welcome.

Love to hear from you hobbyists and students about your first RISC-V system bring-up experiences. Love to hear from you educators about how you use RISC-V in FPGAs in your computer engineering classes.

Love to hear from you @pulp_platform @regymm0 @samsoniak @splinedrive @suarezvictor @sylefeb @tcal_x @theaclay @tnt @trenzelectronic @ultraembedded @willflux @wren6991 @YosysHQ . Love to hear from you wonderful RISC-V in FPGA systems enthusiasts I have accidentally overlooked.

Love to hear from you @hasheddan @jamesstinejr @LucaBeniniZhFe @matthewvenn @micko_mame @mithro @moonbaseotago @nachiketkapre @rsnikhil @obijuan_cube @obr2021 @oe1cxw @olofkindgren @openhwgroup @orangecms @philipfreidin @pipelinec_hdl @PsychogenicTech @ptrschmdtnlsn.

Love to hear from you @1bitsquared @antmicro @ataylorfpga @atomicrules @bjorntopel @bml_hubbard @brouhaha @brunolevy01 @cnlohr @digilentinc @dolu1990 @elaforest @enjoy_digital @florianwoh @fontamsoc @fossifoundation @fpgahelper @fpga_zealot @furan @Gmahovlic @gojimmypi.

Workshop intro: Free registration: Propose a talk (deadline Oct 13):.

Please join us to attend, or to share what is interesting, novel, surprising, frustrating, or fun about your work on RISC-V on FPGAs. Demos encouraged; marketing discouraged. Talks may be live, or prerecorded, lightning talks, or full talks.