Luca Benini
@LucaBeniniZhFe
Followers
2K
Following
34K
Media
37
Statuses
2K
Ferrara, Palo Alto, Ferrara, Zurich... Boh
Joined March 2018
Another RISC-V in an AI accelerator!👍 You need a standard to combat a monpoly...
Excited to announce that d-Matrix has chosen the Andes AX46MPV RISC-V CPU IP for its next-gen Raptor AI inference accelerator! Raptor combines 3DIMC with our high-performance vector CPU to deliver fast, efficient datacenter-scale inference. Read more at: https://t.co/TcL8VfRWXz
1
0
3
This is silicon democratization at work! Toward 'one student one chip' with real tape-outs. So proud of the @pulp_platform team for having pulled this out while I was in sabbatical! 💪
Time to present student chips from this year's VLSI course! 65 students worked in groups of two to improve on our example design Croc https://t.co/iLd70qGh9w resulting in 33 designs. 5 made it, supported through the BMBF project. See e.g. Fluffy below https://t.co/4AOeciY8lL
0
1
6
It was fun. Great discussions afterwards... Going back to EDA, my first passion 😉
#ICCAD2025 is currently underway in the beer capital of the world. Luca gave a plenary talk "End-to-end Open Source Platforms in the era of Domain-Specific Design Automation" and is bringing home some presents😀🍺 . You can find his slides on our website: https://t.co/CglWtFDlfy
0
0
6
This is a fantastic lecture series!
Stanford's "Convex Optimization" Videos & Lecture Notes & more Course 1: https://t.co/emYx7OaLzl Course 2: https://t.co/VopeG1xYkd
0
0
0
Not easy... but 2M is feasible today in EU!
chipmind.ai
AI agents to speed-up development of chips, design and verification, collaborative, custom and confidential with open-source EDA tools.
Show me someone who is investing 20 Million USD in a European Chip Design Tool company. Oh yeah. Ericcson.
1
0
3
Real tech at work! @pulp_platform powered!👍
Greetings from #BioCAS which is currently underway in Abu Dhabi. Here is Sebastian with a "Live Demonstration: Wearable Edge-AI Meets Real-Time Saccadic Eye Movement Classification" using the GAPses smart glasses for a real-time human machine interface.
0
1
6
Addressing critical interconnect reliability issues!
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication.
0
0
5
This is the future of technology AND architecture! Super exciting... a completely new design space. So many new opportunities! 🤠😎
Here is "CMOS 2.0 - Redefining the Future of Scaling", a joint effort with Imec @imec_int & KIT proposing to revisit the functional scaling paradigm leveraging recent developments in advanced chip manufacturing, i.e. 3D wafer bonding & backside processing https://t.co/iUlcUpkhGJ
0
1
10
This is a significant milestone for several reasons (1) First 7nm TSMC shuttle offered at Europractice, (2) it is a large multiB transitor chip, multi TOPS, (3) First 7nm chip entirely made with open source EU IPs , (4) fully #riscv . I am proud of the team that pulled it off!
Here is Picobello https://t.co/33aaKUKmNR, the Swiss way of saying "Everything is great", our latest ASIC in TSMC 7nm taped-out as part of EU Pilot @pilot_euproject through the TSMC Academic Program supported by Europractice. It features many Snitch cores and FlooNoC @fischetim.
0
0
10
Great!
Congratulations to Philip who received The Best Poster Award at The International Artificial Intelligence Summer School in Tuscany. Find his poster "Extreme-Edge AI on PULP: Scalable Intelligence Under Tight Platform Constraints" on our website: https://t.co/ve98kvD0jp
0
0
2
Extremely interesting! Also very well aligned with the @pulp_platform direction, leveraging #RISCV matrix extensions in many-core clusters.... Programmability+efficiency is key!
0
2
6
The PULP ultrasound army 💪
Andrea, Christoph, Federico, Sebastian, Giusy, Cedric & Sergei are currently attending IUS conference in Utrecht https://t.co/orYlo30t7v. Below Cedric and Federico presenting their posters and us discussing future collaboration with Jonas, Martin, Jinhao from UBC.
0
0
4
This is a,glimpse in the future of embodied Generative AI. I am super excited about the hardware platform we'll have to design to enable its long term evolution.
Our joint paper with PBL "RobotxR1: Enabling Embodied Robotic Intelligence on Large Language Models through Closed-Loop Reinforcement Learning" got accepted at the Conference on Robot Learning! See https://t.co/am2eul3qnt Video https://t.co/MxJCBFuElj Code https://t.co/dCYFT2efpo
0
2
9
Super happy and honored for this award! @hotchipsorg is the top event for digital designers, and THE venue to show that open source HW and EDA are coming of age: We got working silicon to prove it! 🙏 to @pulp_platform's team, big 🙏 to @YosysHQ and @OpenROAD_EDA for support!
Great news from #HOTCHIPS2025! Philippe just won The Best Poster award for "34 mm² End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS". Find his poster here: https://t.co/FnFloqMAl1
0
8
31
Lots to learn...
My Google colleagues Norm Jouppi & Sridhar Lakshmanamurthy gave a talk today at Hot Chips on TPUv7 ("Ironwood"). The TPUv7 system offers 9216 chips / pod (42.5 exaflops of fp8), but we can scale across many of these pods to provide multiple zettaflops.
0
1
5
My Google colleagues Norm Jouppi & Sridhar Lakshmanamurthy gave a talk today at Hot Chips on TPUv7 ("Ironwood"). The TPUv7 system offers 9216 chips / pod (42.5 exaflops of fp8), but we can scale across many of these pods to provide multiple zettaflops.
Google presents for the first time ever their TPUv7 block diagram at hot chips conference. TPUv7 (formerly known as TPUv6p, internally called ghostfish) has 8 stacks of HBM3e memory, 4 medium size systolic arrays and be connected in a 3D torus with a scale up world size of up to
25
104
937
As a long time JRR Tolkien fan, I really relate to this... the day an AI model will be able to crearte a body of literature and imaginarium like Tolkien's, I will be fully ready to admit superintelligence has been reached, at least in literature... interesting times! 🤩
I am (slowly) re-reading the Tolkien legendarium (of which Lord of the Rings is a small part). The whole body of work is so incredible and there's nothing else like it... it dilutes other worlds of fiction. Wait - your story doesn't have a comprehensive history/mythology spanning
0
0
2
We are really hellbent to achieve full FPU utilization! ! Maybe too much? 😏
And here is Luca @lucacolagrande3 at #ISLPED2025 in Reykjavik presenting his poster “Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration”. Check out the paper: https://t.co/KD6q4zu1OI
0
2
10
This is the last missing element to make @pulp_platform MCU cluster robust vs soft errors. Protecting memory and cores is not sufficient. You must also protect the low-latency interconnect between them! This paper shows how!
We propose "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" extending Open Bus Interface by combining TMR with error correction codes for critical signals https://t.co/rZer5KhA8K
@MikeRogenmoser @Ang__93
0
4
14
We propose "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" extending Open Bus Interface by combining TMR with error correction codes for critical signals https://t.co/rZer5KhA8K
@MikeRogenmoser @Ang__93
0
3
16