Sylvain Lefebvre
@sylefeb
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Researcher-maker-hacker focusing on Computer Graphics with a #retro, #fpga gaming twist. Enjoys #3dprinting and #electronics. Created @iceslapp and #Silice.
France
Joined September 2010
1/ @tinytapeout 7 just closed and these two tiles host my design! If it works, it will generate explorable terrain 'voxels' similar to the VoxelSpace Comanche 1992 game engine.
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RT @passivestar_: The new Gabor noise in Blender 4.3 looks really promising for quickly creating some sick stylized shapes ✨ .
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RT @exppad: Want to use #WebGPU together with #SDL3?. After recently upgrading #sdl2webgpu, I introduce #sdl3webgpu, little SDL3 extension….
github.com
An extension for the SDL3 library for using WebGPU native. - GitHub - eliemichel/sdl3webgpu: An extension for the SDL3 library for using WebGPU native.
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RT @WillFlux: Beginning FPGA Graphics now covers @RadionaOrg #ULX3S (ECP5) in addition to the @DigilentInc Arty / Nexys Video and iCEBreake….
projectf.io
Welcome to Exploring FPGA Graphics. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and...
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RT @duke_cpu: It’s a #COMET! ☄️ .The #digital DEC705 is a gate array made in the late 1980s. Enjoy the awesome microstructure! https://t.co….
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RT @matthewvenn: In case you missed it, @tinytapeout now supports analog and mixed signal!.
zerotoasiccourse.com
Tiny Tapeout 6 marked a significant milestone by introducing support for analog and mixed-signal ASIC designs. This innovation opened up a world of possibilities for open-source chip development,...
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RT @xavierchermain: ✨ Real-time rendering of anisotropic specular materials with image-based lighting is challenging due to the complexity….
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RT @jangray: #FPGA 1st Soft RISC-V Systems Workshop:.Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the @risc_v Soft CPU SIG is hosting a free onli….
sites.google.com
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2/ I followed the @tinytapeout approach of doing the entire synthesis in github actions, with #Silice seamlessly integrated in the mix. Write your code, commit+push, and get back an ASIC design ready to submit to Tiny Tapeout !.
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1/ If you feel adventurous and want to try both @tinytapeout (make your own chip!) and #Silice I prepared a template for tt09 (61 days to go!). Be warned: I am waiting for my tt07 and tt08 designs to come back to realize my mistakes 😅.
github.com
Submission template for Tiny Tapeout 9 - Verilog HDL Projects - Silice - sylefeb/tt09-silice-template
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RT @WillFlux: I've created a series on RISC-V assembler for software developers. The first part introduces #RISCV, then looks at load immed….
projectf.io
This series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and...
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RT @nand2mario: The first version of GBA core for Tang FPGA is ready 🚀🚀. It's early stage - only some games are working, no save-to-sdcard….
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RT @MittringMartin: NVIDIA’s Tech: Finally, Real Time Ray Tracing! (Episode 900 Special!) via @YouTube.
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