What is the state of current European chip design initiatives, challenges in recruitment, productivity, technology access & strategic opportunities with universities? See "Improving Chip Design Enablement for Universities in Europe – A Position Paper"

#ESSSERC2025 will soon take place in Munich. See us for "A 410 GFLOP/s, 64 RISC-V Cores, 204.8 GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN" on Sept 10, 14:10 in Room 1601 @yichao_zh

Here is our joint paper with Jagellonian University & Politechnika Wrocławska "One Shot vs. Iterative: Rethinking Pruning Strategies for Model Compression" evaluating one-shot & iterative pruning strategies, addressing a gap in NN optimization research

Our paper "Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC" has just been published in IEEE Transactions on Nuclear Science. Find it or @MikeRogenmoser

Here is "BioGAP-Ultra: A Modular Edge-AI Platform for Wearable Multimodal Biosignal Acquisition and Processing" an improved BioGAP with increased on-device storage, better wireless connectivity, enhanced number of signal modalities & analog input channels

We are delighted to see our joint paper with Mahdi and Alessandro @vanelliale "A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN" accepted at GlobeCom 2025 GitHub: @MarcoBertuletti @yichao_zh

2/2: During the HeiChips 2025 Summer School hackathon, Diyou managed to put a 32b Snitch core into the available area and now we are working on the backend. This project will be taped out in IHP130 technology in the following weeks 😀 .

1/2: Diyou recently attended the HeiChips 2025 Summer School organized by Dirk Koch from the Heidelberg University. The school introduced LibreLane, an open-sourced ASIC flow. Check it out:

The slides from Philip's IEEE #COINS2025 talk "A Multi-Modal IoT Node for Energy-Efficient Environmental Monitoring with Edge AI Processing" are now available online:

Last week, the Electrical and Electronics Institute EEI of Thailand paid the Microelectronics Design Center a visit to talk about IC Design and Test in research and academia. Arianna, Beat and Zerun were happy to welcome them.

We would like to introduce our new PhD student Maoyuan who works on fault-tolerance mechanisms and small language model acceleration for PULP vector processors. Welcome to the team, Maoyuan!

Greetings from the EEML @EEMLcommunity Summer School in Sarajevo 🇧🇦 where Cristi @CristiCioflan presented his work on Federated Continual Learning for Nano-Drone Swarms:

"A 66Gbps/5.5W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks" addresses issues with scale-up of beyond 5G transmission bandwidth & number of subcarriers, i.e. throughput, energy efficiency & lifetime of BS HW components: @MarcoBertuletti

IEEE COINS 2025 conference just took place in Madison, Wisconsin. Our Philip was there presenting his work "A Multi-Modal IoT Node for Energy-Efficient Environmental Monitoring with Edge AI Processing”. Check out the paper & the pics from the event below.

RT @LucaBeniniZhFe: We are really hellbent to achieve full FPU utilization! ! Maybe too much? 😏.

RT @LucaBeniniZhFe: This is the last missing element to make @pulp_platform MCU cluster robust vs soft errors. Protecting memory and cores….

We propose "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" extending Open Bus Interface by combining TMR with error correction codes for critical signals @MikeRogenmoser @Ang__93

To fully leverage the higher available bandwidth of shared L1-memory clusters & achieve peak FPU utilization on memory-intensive kernels we propose "TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads" See

And here is Luca @lucacolagrande3 at #ISLPED2025 in Reykjavik presenting his poster “Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration”. Check out the paper:

Greetings from #ISLPED2025 in Iceland! Yesterday Frank chaired an Energy efficient computing and storage session. And our CVA6 & Snitch got mentioned in the talks GenSoc: A Multi-Agent-Assisted SoC Generation Methodology and Transistor-to-GDS Reliability Analysis in Sub-3nm.