Another Agilex 5 Live Stream this Friday!.We’re diving deeper into the FPGA AI Suite on Agilex 5—how the DLA software uses CSRs to run AI model inference. Huge thanks to @AlteraFPGA_ for the support—come hang out!.

Here is a Python notebook using Cocotb to demo the Agilex 5 FPGA with AI‑optimized DSP in Tensor Mode!.It runs a Sobel top + right edge filter fully pipelined in a single DSP. You can tweak the coefficients and try your own computations. 🔗

Got the Altera AI-Optimized DSP running in Cocotb (Python + vsim)! After some digging on the control sequence, it's now simulating two Sobel edge filters at once on a single DSP block. Live demo this Friday—tune in to see it on Agilex 5 FPGA:.🔗

Going live Friday with a demo on the Altera FPGA AI Suite + Agilex 5! We’ll compile ONNX models, show off the new DSPs, and demo on-board edge AI. Huge thanks to @AlteraFPGA_ for supporting this stream—come hang out!. #FPGA #AI #Agilex5.

RT @sundancedsp_inc: 🚀 Just published: “Understanding FPGA Boot Sequence”.How Ultrascale FPGAs boot up? This guide the process from reset t….

Checking out Altera’s new AI-optimized DSP in Agilex 5—each runs two 10×8-bit DOT products with preloaded kernels and shared exponent for FP32. Perfect for ML or vision. One DSP should handle two 3×3 Sobel filters (top & left) for edge detection.

RT @regymm0: Thanks @crowd_supply for the support, my PYNQSDR HAT, a AD936X SDR extension card for the PYNQ-Z1 board, is now at pre-launch!….

Just got an Agilex 5 E-Series dev board from Altera—seriously impressive hardware. FMC, SFP+, HDMI, DisplayPort, PCIe, 24 GB DDR4, and a free Quartus Pro license. What would you want to see demo’d on it?.AI? PCIe? SDR? MiSTer?.🔗

RT @ATaylorFPGA: FPGAs excel at image processing applications. I have just released a white paper which talks all about image processing wi….

Did an under 13 minute MicroBlaze V any% speedrun on the AMD Spartan UltraScale+—from launching Vivado to running a hello_world app out of BRAM. Builds on last week's live demo, but my offline speedrun did much better without streaming software 😁.

RT @enjoy_digital: 🚀 White Rabbit support for the LiteX M2 SDR is shaping up nicely!. First lock of the LiteX M2 SDR design as a WR Slave t….

RT @fpgahelper: It's not too late to back the @Terasic_FPGA Atum A3 Nano campaign on @crowd_supply . The latest update has links to the rec….

IODDRs on AMD UltraScale+ FPGAs map to IOSERDES during tech mapping, which can make tri-state tricky. To drive T with proper IOB FF timing, add a second ODDR—this maps directly to special IOSERDES logic. How often do you use IODDR, IOSERDES, or RXTX_BITSLICE in your designs?

Built a HyperRAM AXI4 PHY for a future MicroBlaze V video—first SUP+ live demo tomorrow!.Runs at 200 MHz and uses <2% of a small AMD Spartan UltraScale+. Prefetch & more coming soon. Git repo:.🔗

Feel free to read the Dissertaton:.

When using a smaller AMD Spartan UltraScale+ FPGA, AXI4 SmartConnect can consume a surprising amount of resources. Manual tuning—like removing pipeline registers and LUTRAM FIFOs—can drastically reduce area (with some performance tradeoff). Here’s default vs. stripped-down:

RT @digikey: Maker Blog - A Guide for the #ESP32 Microcontroller Series . More here:

Live MicroBlaze V Speedrun!.Join me as I setup the built-in soft RISC-V processor for the new AMD Spartan UltraScale+ FPGA with Vivado 2025.1.

AMD sent me a Spartan UltraScale+ dev board! The license and board files are included with Vivado 2025.1. Any suggested connectors for MikroE, PMOD, Arduino, Pi Hat, or HSIO (SYZYGY) to try? .The MikroE catalog is H U G E !.AMD blog post:

I passed! .Here are my slides:.