Olof Kindgren
@OlofKindgren
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No longer active here. Moved to other similar platforms
Joined November 2011
Kick-out-the-nazis-from-our-online-communities-day is coming up in less than a week. But since this platform is nowadays run by such people I will choose to let myself out instead. You can easily find me on other similar platforms if you want to hear about SERV and FuseSoC.
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RT @FossiFoundation: Second week of November and we have a brand new El Correo Libre for you all. This time we will learn about creating gr….
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RT @ATaylorFPGA: Professional FPGA development uses scripting more often than it uses a GUI. I just created a Hackster project which looks….
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The illustrious @ATaylorFPGA just released an article on @Hacksterio on how to get started with FuseSoC. An excellent read and highly recommended for anyone looking for a well-written and straight to the point FuseSoC introduction. Thanks Adam!.
hackster.io
Building FPGA designs with FuseSoC to enable rapid retargeting of code between AMD FPGAs
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RT @fpgahelper: Altera "Logic Elements" are roughly comparable to AMD's "System Logic Cells." This makes things simpler. I'm perplexed by L….
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Phew! That took longer than expected, but now FuseSoC 2.4 is finally released. As always, there's a number of bug fixes and convenience features. The big new feature is EDAM filter functions which you can read about in the docs Enjoy!.
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RT @hipeac: Did you catch the news about the flexible RISC-V processor developed by @Pragmatic_ltd's Emre Ozer, a longtime HiPEAC member, a….
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Haha! Looks like I'm down with the kids :D.
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I just updated the award-winning video gallery with the latest FuseSoC video from ORConf. And what's more important, I managed to fix the CSS after spending like four hours trying to make two div thingies the same height.
award-winning.me
Watch Award-winning Videos
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RT @jangray: #FPGA 1st Soft RISC-V Systems Workshop:.Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the @risc_v Soft CPU SIG is hosting a free onli….
sites.google.com
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If you need something really small and easily bendable, I'm your guy!. Should add that to my Tinder profile.
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Happy to finally reveal a project that @qamcom, @Harvard and @Pragmatic_ltd have worked on for the past two years, creating the first ever fully programmable, general-purpose SoC on printed electronics. And yes, of course it uses the award-winning SERV! :)
qamcom.com
Olof Kindgren published in Nature with Pragmatic and Harvard Highlighting a joint project for pioneering semiconductor applications in wearables, healthcare devices and smart packaging Qamcom has...
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RT @fpgahelper: And in response to the burning question on everyone's mind, we now know that you can fit 1327 RISC-V cores in a single Agil….
corescore.store
an award-giving benchmark for FPGAs and their synthesis and P&R tools
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RT @fpgahelper: Of course it is also available on the obligatory FuseSoC Blinky project by @OlofKindgren . https://t….
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RT @fpgahelper: You can also run the VeeRwolf reference platform from @CHIPSAlliance on Agilex 5. In fact you can run 18 of them on it if….
github.com
FuseSoC-based SoC for VeeR EH1 and EL2. Contribute to chipsalliance/VeeRwolf development by creating an account on GitHub.
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RT @fpgahelper: With this LiteX port by @enjoy_digital you can now run Linux on a soft RISC-V core on Agilex 5.http….
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RT @fpgahelper: @AlteraFPGA_ Agilex 5 is making its way into open-source projects so you have even more examples and resources to help you….
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RT @AlteraFPGA_: Agilex 5 was recently added to the CoreScore leaderboard at 1327 SERV cores. SERV is a tiny bit-serial #RISCV core devel….
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