✈️🏨🚗 RISC-V Travel Fund Alert! Do you need support getting to the RISC-V Summit North America?. Our Travel Fund helps open source developers attend events they’d otherwise miss due to a lack of funding. 📌 Must be an active RISC-V contributor.📌 Covers airfare, lodging, and

📢 @GlobalFoundries' acquisition of @mips_riscv will expand its portfolio with cutting-edge RISC-V processor IP and software tools for real-time computing in autonomous mobility, industrial automation, datacenter, and intelligent edge applications. Read the announcement here:

RISC-V is poised to challenge long-standing technologies in HPC. In his talk, @EPCCed’s Nick Brown outlines the unique advantages RISC-V brings to high-performance computing, highlights progress and key initiatives, and discusses what’s still needed for broader adoption. He also

⏰ The countdown is on! #RISCVSummit North America returns Oct. 22–23 in Santa Clara, CA. Plus, the final Call for Proposals deadline is coming up on Friday, July 11! Submit your talk here: Join the global RISC-V community to explore cutting-edge

️RISC-V International CEO Andrea Gallo joined @DanielNenni on SemiWiki to talk about the incredible momentum behind RISC-V. 🎧 Daniel summed it up:. “Andrea describes the substantial impact RISC-V is having in mainstream and emerging markets. AI is clearly a key part of this.

Automotive technology is evolving fast. @OmdiaHQ’s Edward Wilford breaks down:. - The shift toward general-purpose compute, which has blurred the lines between automotive and industrial applications. - Software-defined system revolutions across industries, anywhere where

#RISCVSummit North America is approaching fast! Join the global RISC-V community from Oct. 22-23 in Santa Clara, CA, to shape the future of open computing. ✅ Register: .🎤 Submit your talk by Friday, July 11: #RISCVEverywhere

“Demand for software defined vehicles, data center infrastructure, and industrial automation is driving growth for custom silicon.”. @mips_riscv and @Cyient have partnered to develop domain-optimized ASIC and ASSP solutions, leveraging the MIPS Atlas portfolio of advance

.@MavenSilicon is now an Approved Training Partner of @AlteraFPGA_’s Solution Acceleration Partner (ASAP) Program!. Through this collaboration, participants will learn how to design advanced RISC-V Chips and RISC-V software applications using Altera FPGAs and boards. Learn more

RISC-V startup @incoresemi has unveiled its SoC Generator platform, a deterministic automation tool that slashes SoC design time from months to under 10 minutes. Built to accelerate RISC-V innovation, this is a major step forward for faster, more flexible SoC development. Learn

Cloud-based RISC-V servers are here. Fabien Piuzzi of @Scaleway shared how their team launched the first cloud-based RISC-V offering. The session covers: .🧩 The motivation behind the project .⚙️ Technical & deployment challenges .🔮 What’s next for RISC-V in datacenters. 📺

Post-quantum cryptography meets RISC-V! . TYRCA delivers a 94–96% speed-up for HQC algorithms using a tightly-coupled accelerator architecture. 📽️ Check out the short walkthrough video and the project: #RISCVFeaturedWork by Alessandra Dolmeta, Stefano Di

Over 13 billion RISC-V cores are now in the world, fueling breakthroughs in AI, wireless, automotive, data centers, space, IoT, and beyond. With thousands of engineers shaping the future of open computing, there's never been a better time to connect. This October 22-23, join

🚀 RISC-V is making strides in space, with several missions already flying it. @ESA’s Lucana Santos recently shared updates on ESA’s expanding portfolio of RISC-V SoCs, growing RISC-V adoption in space systems, and future-ready designs for flexibility and scalability. What’s

📅 Join RISC-V and Infineon on September 9, the week of IAA Mobility, for The RISC-V Automotive Conference 2025! . As the automotive world gathers in Munich, this event will spotlight the growing momentum and opportunities around RISC-V. Join industry leaders for keynotes,.

The future of RISC-V software is taking shape. and it’s happening fast. In this new #TechTalk, industry leaders dive into the critical importance of building a consistent and collaborative software ecosystem for RISC-V. From compilers and firmware to enterprise-ready operating

.@SiFive Chief Architect and Co-Founder Krste Asanovic takes us back to the origins of the RISC-V ISA and shares how it’s grown into a global force over the past 15 years. From embedded systems to high-performance computing, Krste highlights why RISC-V is shaping the future of

RISC-V Summit China 2025 is just around the corner with a standout keynote lineup. Register for free and be part of the global movement driving the future of open computing!. 🧠 Topics include:. - Scaling RISC-V for AI, robotics, and datacenter workloads.- Commercialization of

The RISC-V International team is at #OSSummit in Denver! . Join us at 11:00 AM & 11:55 AM in Room 2H for two open RISC-V discussions or at the RISC-V x Yocto Mini Summit tomorrow at 9am >

At the #RISCVSummitEurope, leaders from Akeana, Beijing Institute of Open Source Chip, @CEA_List, ESWIN, @Siemens, @Tenstorrent, @Thalesgroup, and @VentanaMicro explored how #RISCV is powering next-gen boards, chips, consumer tech, and more. 🎬 Watch the interviews here: