Check out this cool animation done with our 3D @Blender+@KiCAD_pcb visualization flow, showing Signal Integrity testing of our RDIMM DDR5 Tester board, involving #openEMS-driven simulation and comparing results with VNA measurement: https://t.co/JoZvPAbnYc

In our 2nd @FossiFoundation #ORConf talk, we'll show recent updates in the steady progress towards UVM support, constrained randomization support, enhancements to coverage reporting, and improved facilities for power estimation workflows https://t.co/ylWCpqLl9V

Join our @FossiFoundation #ORConf talk where we demonstrate a complete set of open source, vendor-agnostic tools allowing to automatically overview, document and analyze digital design development: Topwrap for SoC aggregation, PeakRDL, uvmdvgen, Testplanner, Coverview & @renodeio

You can now simulate and test complex low-power mesh IoT systems in @antmicro's open source Renode, such as home automation solutions, based on the @siliconlabs Wireless Gecko Series 2 SoCs, with their built-in multi-protocol radio connectivity features:

Read about the recent improvements to Verilator's RTL coverage reporting, including optimized coverage computation process, enhanced branch and toggle coverage, and faster report generation for different types of coverage: https://t.co/JWAbDqxabH @CHIPSAlliance @FossiFoundation

Once again Antmicro is proud to sponsor @FossiFoundation's ORConf. Expect talks on our recent updates in advancing design verification with Verilator and a complete open source tooling workflow for RTL register description/software/testbench generation and IP aggregation

Visualize data flow complexity with Pipeline Manager: now with multi-graph view, granular control of node structure and styling, and easy interfacing with a server or (another) website with JSON-RPC messages to create interactive UIs with diagrams based on your spec

Introducing a customizable In-Circuit Testing platform complemented by our Protoplaster framework for automated, repeatable and efficient testing. See how this open source, modular setup was applied to our @NVIDIA Jetson Orin Baseboard and how to tailor it for any platform:

Our RDFM framework now supports both rsync and xdelta differential algorithms, allowing you to choose the method of generating delta updates depending on your needs. Read about xdelta implementation & see how to take full advantage of RDFM's capabilities: https://t.co/CHDQ6dSIB2

Antmicro's Open Soure Jetson Orin Baseboard now supports a dedicated OCuLink Expansion Board, allowing you to use OCuLink cables to wire up various high-bandwidth PCIe devices, such as high-resolution cameras and NVMe storage: https://t.co/QHvLZaxdKs

In @Renodeio, you can now test the embedded system you are designing based on the @Arm ARMv8-A @RenesasGlobal RZ/G2L MPU - try it with Linux and @ZephyrIoT demos running on its two dedicated processors: https://t.co/2TYsqSmJUm

We introduced automatic clock gating to the @OpenROAD_EDA ASIC design toolchain for faster iteration and more power-efficient digital design. Read how you can easily reduce dynamic power consumption in your chip using open source tools: https://t.co/qWpZ5BUG8M

Learn about the recent improvements in our openEMS-driven Signal Integrity simulation flow, featuring adaptive discretization, differential pairs and updated @Blender visualizations with CI-friendly, command line pipelines: https://t.co/JoZvPAbVNK

We’re excited to launch AutoML for Embedded, an open-source tool co-developed by ADI and @antmicro that simplifies building and deploying machine learning models on edge devices. Explore the tool and start building smarter at the edge: https://t.co/94QfaWMgE0

By combining SAIF wave format support in Verilator with the @OpenROAD_EDA toolchain, we provide a flexible, open source-driven solution for analyzing signal activity and optimizing power efficiency in digital design: https://t.co/f6eSMTPRIq @Google @CHIPSAlliance

Thanks to our collaboration with @adi_news, you can now use AutoML in Kenning to quickly find and deploy optimized models for ultra low-power devices with AI accelerators. Read about the improvements that enabled support for MAX78002 CNN accelerator in Kenning and @ZephyrIoT:

Using @renodeio's extensive execution tracing capabilities and the new integration with Coverview you can now track code coverage, without additional instrumentation of the code, and aggregate results into a unified, interactive dashboard:

At this year's @DAC_Conference we will demonstrate how SystemRDL combined with open source tools such as OpenTitan's testplanner and uvmdvgen, and Antmicro's Topwrap SoC aggregation & Pipeline Manager can be used to maintain a coherent system state and ensure effective