Thanks to our collaboration with @adi_news, you can now use AutoML in Kenning to quickly find and deploy optimized models for ultra low-power devices with AI accelerators. Read about the improvements that enabled support for MAX78002 CNN accelerator in Kenning and @ZephyrIoT:

Using @renodeio's extensive execution tracing capabilities and the new integration with Coverview you can now track code coverage, without additional instrumentation of the code, and aggregate results into a unified, interactive dashboard:

At this year's @DAC_Conference we will demonstrate how SystemRDL combined with open source tools such as OpenTitan's testplanner and uvmdvgen, and Antmicro's Topwrap SoC aggregation & Pipeline Manager can be used to maintain a coherent system state and ensure effective

Find out how we enhanced Verilator's hierarchical mode for better performance and scalability & join us at @DACconference to learn more about this and other recent improvements we introduced to Verilator: @CHIPSAlliance

RT @CHIPSAlliance: What does a collaborative open source chip design environment look like?. At DAC, CHIPS Alliance’s Robert Mains moderate….

Join us at @DACconference for the BoF Open Source EDA Session to learn about latest updates in Verilator for architectural exploration, verification, and testing: improved hierarchical mode, measuring coverage, SAIF support and more. @chipsalliance

We released a standalone, enhanced version of @lowRISC OpenTitan's testplanner with test result interlinking and more for improved digital design & DV tracking. Generate testplans & simulation result tables, explore our @CHIPSAlliance I3C project example:

RT @CHIPSAlliance: New Blog: Interactive #RTL Coverage Dashboards for #VeeR and #Caliptra. In this post, @antmicro walks through how Cover….

The scalable Audio Latency Tester for developing AR/XR systems is easily embeddable into more complex measuring and testing setups involving both audio & video. Use it with a PC or an embedded platform like our open Jetson Orin Baseboard:.@NVIDIAEmbedded

We improved #Verilator's hierarchical mode in terms of verilation and compilation times, resource usage and scalability to enable faster-turnaround ASIC design flows for complex designs. See how we can extend Verilator for your use case: @CHIPSAlliance

New revision of Antmicro's highly popular Open Source Jetson Orin Baseboard is back in stock at @CircuitHub. Same small footprint with support for both @Nvidia Jetson Orin Nano and NX SoMs in Super mode for an extra edge AI compute boost

We extended @Google Pigweed SDK to support Bluetooth on @Arm Cortex-M33 @NXP MIMXRT595 MCU for use in constrained wireless devices. Check out the PoC using 1x MIMXRT595 MCU runing Pigweed and 3x @NordicTweets nRF52840 SoCs with @ZephyrIoT and @renodeio

See how you can benefit from full-system simulation of CHERI-enabled hardware in @renodeio thanks to its integration with MPACT-Cheriot, and try a co-simulation demo of a complete CHERI-based @risc_v platform: @Google.

Discover how we improved @renodeio's performance on 64-bit @Arm-based machines such as @Apple Macs, @Raspberry_Pi and server infrastructure with native 64-bit Arm host support, now available for both macOS and Linux:

RT @renodeio: Watch our RISC-V in Space talk on using Renode to create digital twins of platforms, run unmodified SW in multi-node heteroge….

RT @CHIPSAlliance: The whitepaper is here! Designed to demystify the current state of #openhardware #opensilicon, outline the challenges ah….

See how we extended @renodeio with new complex DPI-based HDL co-simulation scenarios and find out how we can help you accelerate FPGA & ASIC design, development and testing with a flexible, deterministic co-simulation environment @MicrochipTech #Verilator

We return to @TheAmpHour with a deep dive into System Designer + @renodeio and how to conceptualize, simulate and build advanced HW/SW systems from the chip upwards; @ZephyrIoT, an AutoML module in Kenning AI framework, @CHIPSAlliance Caliptra RoT & more