Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer.

@machdyne @DigilentInc @RadionaOrg With bitmap graphics display working, the next few Isle #FPGA Computer updates will cover:. • 2D drawing engine.• Unicode Text Mode.• RISC-V CPU (existing design). Once these components are in place, I'll assemble an initial version of the computer.

Generate videos in just a few seconds. Try Grok Imagine, free for a limited time.

Over the weekend I released the next part of Isle #FPGA Computer covering bitmap graphics. I've added more docs and tests, but I'm still finding the right approach to the Isle blog and working on diagrams.

Some friendly advice from Microsoft on the use of AI in Excel. “Avoid using COPILOT for: Numerical calculations…”

No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday.

@machdyne @DigilentInc @RadionaOrg Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA. Here's a simple example; it could be better, but it's something to build on:

RT @WillFlux: Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentati….

I'm getting to grips with more cocotb tests for Isle #FPGA computer. This new test verifies pixel output end-to-end: address_calc > vram > clut > display. We're not letting any latency issues sneak in. Will be part of Chapter 2: Bitmaps.

@machdyne @DigilentInc @RadionaOrg Part of the Isle #FPGA computer project is explaining my design choices. I hope this is interesting and aids you when working on your own hardware. In the display modes post, I explain why I'm supporting 1366x768, 1024x768, and 1280x720:

Reading through my posts for the first time in a long time, I noticed a mistake. I claimed the IBM System/360 had a zero register, which isn't true! Thankfully, I was on firmer ground with the CDC 6600 designed by Seymour Cray. 🤓.

“RISC architecture is going to change everything.”. Have you seen my seven-part Guide to #riscv assembler? No ads or crappy popups.

Icepi Zero looks like an interesting open-source ECP5 #FPGA dev board. It’s got a decent spec in a small form factor. The only obvious omission is audio out. The big question is, how much will it cost?

@machdyne @DigilentInc @RadionaOrg I don't yet have a complete system to share with you. Getting the design right takes a lot of experimentation; I've hit dead ends several times. I'll gradually introduce components over the coming months. The first part looks at display signals. #FPGA 📺

Isle targets @machdyne Lakritz, @DigilentInc Nexys Video, @RadionaOrg ULX3S, and Verilator/SDL simulation that runs on your PC or Mac. Designs, docs, and test benches are available under the MIT license:

New #FPGA project from me this Friday. Just been validating the HTML and running some final tests. I thought it was time I nailed my colours to the mast. 🚀

Be not afeard; the isle is full of noises,.Sounds, and sweet airs, that give delight and hurt not. 🏝️.

“Word (computer architecture)” on Wikipedia is surprisingly interesting. The influence of System/360 is evident again. The big table of word sizes is engrossing. The Manchester Baby had 32-bit words in 1948, though it only had 32 of them. 🤔

It seems IBM System/360 was the first (significant) architecture to adopt byte addressing in the mid-60s. It's a good thing™, but one to test carefully when designing computer hardware. I don't allow misaligned words, which helps.

Another update to img2fmem, my tool for converting bitmaps to Verilog $readmem & Xilinx coe files. Now supports packed 32-bit & mono images. Seen my recent posts? You've seen the packed 32-bit mono images in action. #FPGA. Find the latest version here:

Two word vs byte addressing bugs were cancelling each other out. The life of the hardware developer! 😬 #FPGA.