486Tang v0.1 is out! 🕹️🚀 A 486SX-class PC on the @SipeedIO Tang Console 138K by porting the excellent ao486 core. VGA graphics (upscaled to HDMI), SB16+OPL3, IDE. Runs early-90s classic DOS games. Grab the release: https://t.co/p0Ac4GWrPw

Introducing z8086🎉, a new 8086/8088 soft core that runs on the original Intel microcode. ~1200 ALMs on Cyclone V, ~2500 LUTs on GW5A, vendor-neutral SystemVerilog. https://t.co/uM52d96xQN

Another #z8086 demo of x86 assembly driving LCD, running on @SipeedIO Tang Console 60K FPGA.

A longer introduction to z8086 - the 8086 soft core that runs the original microcode - and some interesting discoveries building it: ☕⚡ 1. two important formulas in patent are wrong, 2. microcode greatly saves resource, 3. the 8086 interrupt bug. https://t.co/7MMlWn52cp

This is a 0.1 version. It passes all my 16K single-instruction tests and runs small demos fine. But more tests are needed for real application. Feedback and bug report are welcome.

A slightly more sophisticated demo of the 8086 core — driving SPI display 😀

Boot process of "blinky": The key signal is FC (1st cycle) and SC (2nd cycle), as called in Intel doc. FC marks the first byte of each instruction on "q_bus". The first instruction here is 0xEA (long jump to F000:0000). 2nd instruction is 0xFA (CLI). "uaddr" is microcode address.

A satisfying blinky demo, powered by my 8086 core executing the original 8086 microcode.

Great progress 🎉 — the 8086 core now passes all 16,150 single-instruction tests and all 17 short-program tests. Even in its current unoptimized state, it fits in roughly 3,000 LUTs on the GW5A and already runs at 50+ MHz.

Fun tidbits about 8086 μcode, 1. Reg IDs change meaning: e.g. 10100 is SIGMA as src, and tmpaL as destination 2. N and R are the same register 3. IP (or PC) does not point to the next instruction 4. Almost all arithmetic instructions share the same 4 lines of microcode (008-00B)

✨ Features: • 21-bit micro-instructions broken into readable fields • Hover tooltips that decode every field • Click to jump between routines • Browse by x86 instruction • Short jump visualization • Dark/light themes

🔬🔥 Just posted: 8086 Microcode Browser - a fully interactive viewer for your retro enjoyment. Explore all 512 micro-instructions and see exactly what the CPU does across the ~130 cycles of a MUL instruction (or any other instruction). https://t.co/kCggJhm37Z

Weekend of hacking: I’m up to 90.6% test coverage, with only the tough parts left — String instructions Interrupts Multiplication and division Here’s the latest block diagram of the core.

8,531 / 16,150 test cases now pass on the 8086 CPU — over half of the instruction set implemented. The design is shaping up nicely, and it’s still only about 1,200 lines of Verilog so far. 😄

Last minute update #TinyTapeout. TinyGPU v2.0 now support Texture mapping. Tex res 256x256, 4-bit. Texture mapped models run 33% slower than the flat shading version. The project uses 66% of 4x4 tiles, around 240k transistors. git: https://t.co/ClhiKS89st

Building an open-source FPGA core for the iconic Intel 8086/8088, based on Andrew Jenner's disassembled microcode! Should I focus on education/clarity, cycle accuracy, size, or performance? Let me know.🙋 Some instructions are already working. Let me know your thoughts. 👇

I also made a version with function block and pin names, following Ken Shirriff's 8086 articles. https://t.co/IVDcG0DgOo

Here's the 1984 Intel 8086-S die shot📷. 8086-S is a revision/die shrink of the original 8086 with the 3 µm HMOS II (a type of NMOS). The full (12780x12554, 62MB) is at https://t.co/cGOU82kAUI. This time I improved my stitching scripts, so the whole process took only a few hours.

Decapped this ~40 year old ceramic packaged Intel 8086. This is easily opened with a small chisel in a minute. Turns out to be a “8086 S” die with 3um HMOS-II process.

The microscope was ancient and bought cheap. The stitching software is Hugin. I had to write custom Python scripts as Hugin alignment takes too long for this many images. The whole process took several tries over two weeks and it's a fun learning process. 😄

Worked with many FPGA cores and got curious about actual chips. So here's the first die shot that I took 🔬🎉: Motorola 68HC05L10 from 1993, a 6800-compatible 8-bit MCU. It is stitched from ~450 photos taken with an Olympus BH2-UMA microscope and the Canon M6 camera.