Videos are up from the Third #ChiselLang Community Conference (presented by @CHIPSAlliance)! See: https://t.co/dGJ18vbGAL Note: there are audio issues with four videos and those will be posted once audio is re-recorded.

Do you have a cool project using or building on FireSim or Chipyard? Submit a talk to the First FireSim and Chipyard User/Developer *Workshop*, co-located with @ASPLOSConf 2023 on March 26, 2023! Learn more and submit your work here:

@jackakattack @prithayan Second session is coming in half an hour, the first talk is Hongren Zheng from Tsinghua University/PLCT -- "Implementing RISC-V Scalar Cryptography/Bitmanip extensions in Chisel".

@jackakattack The last talk in the first session is @prithayan and Hideto Ueno of SiFive -- The Next Generation FIRRTL Compiler is Here!

Up next is @jackakattack from SiFive -- Chisel Breakdown 3 (a quick overview of Chisel's internals for developers)

We have solved the technical difficulties so now @jerryzh123 is up!

@jerryzh123 Slight technical difficulties so up now is @ElectronicKiwi from UCBerkeley -- "The formal verification capabilities of chiseltest"

First up at 6pm Pacific is @jerryzh123 from UCBerkeley -- "Constellation, a Open-source Chisel NoC Generator for SoCs"

The Chisel Community Conference 2022 in Shanghai (CCC22) starts in 45 minutes at 9 am China Standard Time, 6 pm Pacific! Zoom link is on the Chisel Github!

Less than 24 hours until our FireSim, Chipyard, and Hammer tutorial at @ISCAConfOrg! As usual, in-person attendees will be given free @awscloud EC2 F1 instances to run these tools hands-on! 1/3

Local FPGA support (@XilinxInc U250) and distrib SW sims are coming to FireSim this week! @KarandikarSagar and @NayiriKr will cover these features at OSCAR 2022 at @ISCAConfOrg on Saturday. Thanks to great work by @davidbiancolin @abejgonza @TimSnyderATX!

Get involved and learn more about @chisel_lang, check out the site at https://t.co/pLrHrWCBMu and @MartinSchoeberl free book at https://t.co/ollMY1o2HU. Also https://t.co/TZTILoXp6E for an interactive lab.

Join us next Tuesday, April 19 at the CHIPS Alliance Spring Event to hear from Jack Koenig, senior staff engineer at SiFive, and other industry experts on open innovation. #RISCV #NoLimits

I'm glad to share our upcoming DATE-2022 paper titled "Twine: A Chisel Extension for Component-Level Heterogeneous Design". Twine is a Chisel HDL extension for heterogeneous design. Source code release is here: https://t.co/j7NeHXEuLF, paper is here: https://t.co/qop4R0Y3TF.

Happy to say I have a fully working C program running on ChiselV, my RV32I @risc_v processor. Wrote a simple library (like an Arduino) to access the GPIO and Timer. Can’t be more satisfied! 🎉 Now, on to having a serial interface! #RISCV #ChiselV https://t.co/PIHhOcN2Za

Thrilled that the sample program from “Digital Design and Computer Architecture” book by Sarah and David Harris now works on ChiselV, my RISC-V core! Chisel is great to build and test hardware designs. @risc_v @chisel_lang #RISCV https://t.co/rQEuL2yPjC

The @CHIPSAlliance Fall Workshop is starting shortly but there is still time to register. There are some great #RISCV presentations so don't miss it.

Join Jack Koenig, Engineer at SiFive, for an update on next-gen SoC design using the Chisel hardware construction language at the @CHIPSAlliance workshop on October 12. Learn more and register here: https://t.co/6rsbRDmCTj #riscv #sifive #opensource #chipdesign

Don’t miss Jack Koenig of @SiFive's session “Chisel Advances for Next-gen SoC Designs” at the CHIPS Alliance Fall Workshop on Oct. 12. Check out the schedule and register today: https://t.co/gNCdQVn80j

Can't wait for the workshop and @jackakattack session. I've been playing with the latest @chisel_lang version and it's amazing.

Don't miss my talk on new features in [upcoming] Chisel 3.5 next Tuesday (Oct. 12) at 8:45 am Pacific Time!