Big news from SiFive: We're launching five new RISC-V IPs in our 2nd Gen Intelligence lineup to accelerate AI — from far edge IoT to the data center! - X160 Gen 2 - X180 Gen 2 - X280 / X390 / XM Gen 2 Learn more 👉 https://t.co/qhIlk6NEi1 #NoLimits

Mill v1.0.0 is out: a better build tool for #Java, #Scala, and #Kotlin. Check it out! https://t.co/21dL2YmMXY

The whitepaper is here! Designed to demystify the current state of #openhardware #opensilicon, outline the challenges ahead, and chart a path forward for everyone from startups to silicon giants. https://t.co/dcUozarIdw

It's absolutely crazy to me that the most exciting Scala projects today are actually happening in the hardware RISC-V space with tools like Chisel rather than the traditional, stronghold domains. And, on top of that, they innovate in chip design.

We have issued an Evacuation Order due to a Tsunami coming to West Berkeley.

For anyone looking, this is the Tsunami risk map for San Francisco on https://t.co/0DkrZjTekn

GREAT DAY TO BE A LONGHORN 🤘

.@ElectronicDesgn shares more on the HiFive Premier P550 development board, featuring a quad-core #RISCV SoC, Imagination GPU, and ESWIN NPU, built for next-gen embedded development. Read all about it: https://t.co/wRDzmza6iW #NoLimits

“If you’re looking to push the boundaries of what’s possible with RISC-V, this could be the test and development platform you’ve been waiting for.” Dave Altavilla shares his take on the SiFive HiFive Premier P550 development board here: https://t.co/EA7GelSdst #NoLimits

📢 The SiFive HiFive Premier P550 development boards are now shipping! Grab one from the initial pre-release batch of 100 Yocto-ready boards via @ArrowGlobal, or wait for the Ubuntu-supported version coming in Q4. Learn more: https://t.co/Vp3TDwXsX5 #RISCV #NoLimits

The SiFive Intelligence X280 is out of this world! ⭐ @MicrochipTech is integrating our X280 64-bit #RISCV cores into the company’s high-performance space-flight computing processor. Read more via @ElectronicsNews: https://t.co/Q12ZJQKIro #NoLimits

DeepComputing is showing an early demo of the new RISC-V Mainboard at the @risc_v Summit in Munich next week. This board uses a @StarFiveTech JH7110 with @SiFive RISC-V CPU cores. DeepComputing is also working closely with the teams at @ubuntu and @fedora on Linux support.

.@SiFive unveils the high-performance, AI-accelerating HiFive Premier P550 RISC-V development board.

📢 New board alert! The HiFive Premier P550 is the highest performance #RISCV development board in the industry. Available through @ArrowGlobal this board enables developers to test & develop new RISC-V applications. Learn more here: https://t.co/FkjwRdKKHg #NoLimits

Watch talks from members on collaborative #opensource projects including Open Se Cura, #Caliptra RoT, #Chipyard, #UVM testbenches in #Verilator & using #FuseSoC w/ VeeRwolf: https://t.co/D8eDWprmvF @linuxfoundation @risc_v @Google @antmicro @verisilicon @UCBerkeley @OlofKindgren

Join the hybrid CHIPS Alliance Technology Update hosted by @Google for talks on #openhardware & collaborative #ASIC / #FPGA development by @intel, @westerndigital, @antmicro, @SiFive and @UMich, following #60DAC. Register: https://t.co/6hJjdefqgG @risc_v @linuxfoundation @60thDAC

We are delighted to hear that Chipyard, an open source framework for agile development of Chisel-based SoCs developed at UC Berkeley, supports several cores from PULP ecosystem. https://t.co/LHecazftRq https://t.co/gslke6Sib6 https://t.co/qknTOTUo4H

Time for SimCommand by Vighnesh Iyer

After some much needed coffee and cookie we are ready for our next speaker @abejgonza presenting ChipYard

Now we have Nayiri Krzysztofowicz talking about HAMMER for reusable design flows