Olof Kindgren
@OlofKindgren
Followers
7K
Following
13K
Media
794
Statuses
12K
No longer active here. Moved to other similar platforms
Joined November 2011
Kick-out-the-nazis-from-our-online-communities-day is coming up in less than a week. But since this platform is nowadays run by such people I will choose to let myself out instead. You can easily find me on other similar platforms if you want to hear about SERV and FuseSoC.
1
0
11
Second week of November and we have a brand new El Correo Libre for you all. This time we will learn about creating graphics on FPGA with @WillFlux, see @ATaylorFPGA having fun with FuseSoC, take a peek at @tnt's ROM compiler and much more. Enjoy! https://t.co/dkh6Fmkx6u
0
7
11
Professional FPGA development uses scripting more often than it uses a GUI. I just created a Hackster project which looks at using FuseSoC to build projects using scripts and enabling rapid targeting of FPGAs. #fpga #embeddedsystems #electronics #embeddedsoftware #engineering
0
17
147
The illustrious @ATaylorFPGA just released an article on @Hacksterio on how to get started with FuseSoC. https://t.co/uocnDY33EQ An excellent read and highly recommended for anyone looking for a well-written and straight to the point FuseSoC introduction. Thanks Adam!
hackster.io
Building FPGA designs with FuseSoC to enable rapid retargeting of code between AMD FPGAs
1
13
65
Introducing Oasis: the first playable AI-generated game. We partnered with @DecartAI to build a real-time, interactive world model that runs >10x faster on Sohu. We're open-sourcing the model architecture, weights, and research. Here's how it works (and a demo you can play!):
1K
1K
13K
Altera "Logic Elements" are roughly comparable to AMD's "System Logic Cells." This makes things simpler. I'm perplexed by Lattice's "System Logic Cells." Using the same terminology with a different definition is confusing. CoreScore by @OlofKindgren is more meainingful.
Comparing the capacity of FPGAs with different architectures can be complicated. Did you know you can fit 18 Very Efficient & Elegant RISC-V cores from the @CHIPSAlliance in a single Agilex™ 5 E-Series FPGA? Read the whitepaper to learn more: https://t.co/udhpt2WN8g
0
2
5
Phew! That took longer than expected, but now FuseSoC 2.4 is finally released. As always, there's a number of bug fixes and convenience features. The big new feature is EDAM filter functions which you can read about in the docs https://t.co/mEAyKVgFeb Enjoy!
0
2
11
Did you catch the news about the flexible RISC-V processor developed by @Pragmatic_ltd's Emre Ozer, a longtime HiPEAC member, and others? Check out this short video of this exciting new development here: https://t.co/bznh2Zgcxs Congratulations to everyone involved in this work!
0
2
8
Haha! Looks like I'm down with the kids :D
0
0
7
I just updated the award-winning video gallery with the latest FuseSoC video from ORConf. https://t.co/VfZ263mOwj And what's more important, I managed to fix the CSS after spending like four hours trying to make two div thingies the same height.
award-winning.me
Watch Award-winning Videos
0
0
9
Läs nyheterna på https://t.co/w3X3LvqVi3! • Fem dagar tidigare • Ingen betalvägg • https://t.co/nE9rYVvoHX • https://t.co/BoYMiAn8Q4
0
1
2
#FPGA 1st Soft RISC-V Systems Workshop: Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the @risc_v Soft CPU SIG is hosting a free online workshop & celebration of the vibrant RISC-V soft processor community. RT/spread the word & join us as attendee or presenter. https://t.co/iKo07N6wg8
sites.google.com
2
26
73
If you need something really small and easily bendable, I'm your guy! Should add that to my Tinder profile.
0
0
8
Happy to finally reveal a project that @qamcom, @Harvard and @Pragmatic_ltd have worked on for the past two years, creating the first ever fully programmable, general-purpose SoC on printed electronics. And yes, of course it uses the award-winning SERV! :)
qamcom.com
Olof Kindgren published in Nature with Pragmatic and Harvard Highlighting a joint project for pioneering semiconductor applications in wearables, healthcare devices and smart packaging Qamcom has...
2
4
43
And in response to the burning question on everyone's mind, we now know that you can fit 1327 RISC-V cores in a single Agilex 5 device thanks to https://t.co/Mw9VmGyVTb also by @OlofKindgren
corescore.store
an award-giving benchmark for FPGAs and their synthesis and P&R tools
0
1
3
Of course it is also available on the obligatory FuseSoC Blinky project by @OlofKindgren
https://t.co/i4MeF5gx2H
1
1
1
You can also run the VeeRwolf reference platform from @CHIPSAlliance on Agilex 5. In fact you can run 18 of them on it if you go to the VeeRwolves branch. https://t.co/sIoTy5xBbT
github.com
FuseSoC-based SoC for VeeR EH1 and EL2. Contribute to chipsalliance/VeeRwolf development by creating an account on GitHub.
1
1
4
With this LiteX port by @enjoy_digital you can now run Linux on a soft RISC-V core on Agilex 5 https://t.co/uiIN3eoIf2
1
2
7
@AlteraFPGA_ Agilex 5 is making its way into open-source projects so you have even more examples and resources to help you get started. Let's look at a few (thread)
1
3
16
Agilex 5 was recently added to the CoreScore leaderboard at 1327 SERV cores. SERV is a tiny bit-serial #RISCV core developed by @OlofKindgren
https://t.co/4LnmgLjbou
#opensource #RISCV
0
3
10