Reconfigure.io
@ReconfigureIO
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The next stage in computing power
UK, TX, CA and NYC
Joined August 2015
Really excited to be able to reveal @lowRISC's closer collaboration with Google and ETH Zurich. https://t.co/UMSGSh7ayI New board members and an exciting development roadmap made possible by the support and funding from Google. Also, we're hiring!
lowrisc.org
We are growing our team to deliver a high-impact, open-source hardware roadmap in collaboration with Google and other industry partners.
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Just merged @golang x/sys module with latest #RiscV assembly code and now the GC works! Successfully built go-Jsonnet and a webserver with Echo( https://t.co/CfvLsKmj82).
@golangnews @jessfraz @SiFive @palmer_dabbelt @justincormack @risc_v @marco_peereboom @labstack #golang
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I can’t believe what I’m seeing! While running a facial recognition pilot, one man (understandably imho) covered himself up. The police forced him to show his face (& then fined him for disorderly conduct). This is dangerous & terrifying.
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Our FCCM short paper is now on arXiv: Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanović. https://t.co/MILrfUyIFv
arxiv.org
This paper introduces a fully free and open source software (FOSS) architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement, routing, and bitstream...
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Not quite the silver bullet, certainly not yet, in compute. Performance v cost (key driver still post-Moore’s Law) is fast being advanced with hardware such as FPGAS & numerous software/architecture developments. #Nanotechnology is speaking louder in compute but has a way to go.
Move over, silicon switches: There's a new way to compute https://t.co/ehv9AaGHsx
#science #nanotechnology #technology
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You might not be aware, but SymbiFlow can synthesize @linuxfoundation #Linux and @ZephyrIoT capable @RISC_V SoCs today. Participate in @GSoC - applications close in 5 days so be fast! - and help us open up #FPGA tooling to accelerate innovation in FPGAs:
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I feel like if @intel and @alteracorp want to really shake things up they should apply their usual love of Open Source to FPGA bitstreams and support open synthesis and place+route for their FPGAs. Sure, patents and IP and stuff, but they've a big arsenal to defend against trolls
Really excited by Project Trellis - https://t.co/9gmuYuRcwY - which aims to create a fully open source toolchain for ECP5 based @latticesemi parts. I already had an ECP5-5G and just picked up the regular Versa board too. This is perfect for some of my pet project plans :)
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One-size-fits-all #investment models don’t suit #Nanotechnology due to horizontal & enhancing/enabling characteristics. Research, government initiatives, collaborations, JV’s, corporate venture, #tech licensing, equity/debt and M&A all need to be considered within a nuanced mix
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Boot SMP Linux on @OpenPiton+ Ariane🚀! The Princeton Parallel Group and IIS ETH are bringing you the first Linux-booting, open-source RISC-V system that scales from single to manycore. Download 1, 2 and 4-core FPGA bit files here: https://t.co/DikNWyDy9R
https://t.co/jpf9P6UXoT
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Find it hard to keep track of all the great Open Source Silicon events? Don't worry. We have collected them all at https://t.co/Q8xcPZ8F49 First up is @LatchUpConf followed by Week of Open Source Hardware (WOSH) together with @risc_v @eurolab4hpc and @pulp_platform
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Microsoft is open sourcing Project Zipline to spur faster implementation in silicon #OCPSummit19
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#FPGA Essential reading. Composing FPGAs and data center resources at scale with Direct Univeral Access.
A communications architecture that makes diverse, large-scale FPGA programming easier? A resource manager that can scale to individual clusters of over 50,000 machines? Read how Microsoft researchers are using abstractions to empower cloud users: https://t.co/CfnTqAracx
#NSDI19
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Today is the best second Tuesday of the month as we once again bring you the @librecores newsletter with the latest news from the buzzing world of free and open source silicon featuring @risc_v @OpenPiton @SpinalHDL @pulp_platform @WesternDigiCTO and more
medium.com
RISC-V Foundation Names Summit SoftCPU Contest Winners
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They've done it. Congrats to @SeraphimCapital portfolio company @iceyefi for the success of their mission. Following ICEYE-X1, the world's first SAR satellite under 100kg in mass, ICEYE-X2's use cases will include flood extent monitoring, vessel detection and field segmentation.
Confirmed - ICEYE-X2 SAR satellite has separated successfully. Communications with the satellite have been established at 19:58 CET, December 3rd 2018. Thank you @SpaceX @SpaceflightInc! Launch success! Read more here:
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.@awscloud has also created a new chip, a “AWS Inferentia,” a latency-sensitive high-throughput processor for #ml inferencing. Supports all major #ai frameworks, can be attached to #EC2 instances and also available with #SageMaker — @ajassy #AWSreInvent2018
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Mission 1 was a huge success. They have secured or have offers for £4m+, continue to engage with our corporate partners, have hired 15 new staff and have set up several new offices in the UK #SpaceTech #Mission2
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Reconfigure v0.18.3 is released 🎉 We're getting closer to adopting our reworked compiler, read more here: https://t.co/5XgAzodyTv
#FPGA #golang #startup #acceleration
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