Hyperthreading is Dead. Major CPU manufacturers (including Intel) are getting ready to abandon SMT hyperthreading completely. It's not as crazy as you think. In fact, Apple, Qualcomm, and Samsung have *never* used Hyperthreading. But why? 🧵

We are hiring multiple PhD students and Postdocs: https://t.co/xMAaBvElnI Are you ready to take your research career to the next level? We are seeking highly motivated PhD students and postdoctoral researchers to join our lab and make a significant impact on real-world

I didn't know one could listen to HF SDR stations from all around the world on a website. https://t.co/o7pYMExsAN

@AMD's Zen 5 powered Ryzen 9950X in the flesh with the core architecture visible.

Just FYI, computer vision papers submitted to IEEE that include this image of Ms. Forsén will no longer be considered for publication

"This patchset takes decoding of a 1080p HEVC clip from 402 fps to 649 fps on an Apple M1." An astonishing ARM assembly patchset: https://t.co/Xhr8l8rArO

https://t.co/04o6MgTzur

Changing otherwise inaccessible memory addresses using the row-hammer attack: https://t.co/6VsnIlQvkN, This attack can flip bits in neighboring DRAM cells.

There is no feeling above closing those tabs after finishing a project

debian+xfce HDD vs SATA SSD: boot time analysis by $ systemd-analyze critical chain

I'd say that's the truth

ZFS file system performs data integrity checking on files and can actually pretect them from any sort of corruption!

Wow, we're under 10k lines of Verilog code for an sv32 rv32ima RISC-V 2-way associative 2 TLB MMU, with GPIO, network, OLED display, audio, 2x UARTs, SD card controller, SPI NOR controller, audio device, SDRAM controller Linux SoC. It's awesome, man.

Are there any debian users with tips about long term maintenance of a desktop debian system? I don't want to end up with a crowded system that breaks every now and then a few years down the line

Has anyone worked on an offline password manager on a uController or an FPGA? I'm trying to design one for myself and it would be good to use some extra ideas

It's never been so satisfying to watch the keys I'm pressing pop up on the screen! I was working on a UART verilog module and to fully test it I am sending the received data back to the computer.

*tries to anonymize my paper* reviewers:

After a brutal 24 month gestation period, my baby finally made it as the cover article.

Talking about how we're making transformers neuromorphic friendly tomorrow with Intel.

Been experimenting a bit today with audio playback from Verilator and using GTKWave in interactive mode. Still a bit slow, but it works