Explore tweets tagged as #verilog
Best Advice: Start learning Verilog HDL and FPGA with Vicharak Shrike lite for 4$. Believe me there is no other affordable FPGA dev kit than this beast.
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Dreaming up a CPU is easy. Verifying it actually works is the nightmare. During my time at Google working on TPU projects, I learned that you don't just "write Verilog." You have to build a complete ecosystem. I’ve built a custom CPU from scratch. Here is how I test it using
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finally got this FPGA delivered, now going to try synthesize our Verilog LLM implementation into this chip the idea is to avoid redundancy of generic cpu/gpu and synthesize LLM directly into silicon to achieve better performance it works in simulation, and if it works on this
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Unwrapping TPUs Day 4 —> we made a tiny tiny tiny TPU . Today we implemented a 2x2 Systolic Array from scratch in RTL! Enter the Verilog beast :O
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Unwrapping TPUs 🎄: Day 14 x 14.5 - We close the loop on our verilog implementation from last week w full forward pass! - We emailed Cliff Young (one of the original TPU architects) with some questions .. and he generously wrote back !
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Unwrapping TPUs: Day 4 🎄 Proof of concept inference chip We implemented a tiny tiny TPU with super minimal verilog (hardcoded weights and activations). It was hype though
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8,531 / 16,150 test cases now pass on the 8086 CPU — over half of the instruction set implemented. The design is shaping up nicely, and it’s still only about 1,200 lines of Verilog so far. 😄
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ever wondered how the chips inside rockets, robots, and routers are designed? > this book walks you through digital circuits, Verilog, and VHDL from scratch. > perfect for hardware hackers, embedded engineers, and anyone who wants to go beyond software.
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MSX3の方針メモ MSX3の開発は、MSX2＋＋などの開発で遅れていますが、MSX2＋＋などで作成したVDPやSoundチップのVerilogを使うことを前提に、順番に進めることにしています
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building Gateflow -Cursor for System Verilog updates UI improvements Waveform viewer version 0.1 ( still ass imo) this waveform viewer was a pain in the ass to build but a new version is already on the way. current issues need to be resolved where the waveforms are not
we are building Cursor for DSP & numerical computing. version 0.1 demo is here rough edges, but it works. we are shipping fast and pushing toward a better way to do science-based computing. actively looking for pre-seed partners who get the vision. tag investors, angels, or
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Feel like Flash/Verilog system models? Then here… just crazy f***ing stuff. https://t.co/O1ch5lrCtb KianV for fuckers!
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Unwrapping TPUs Day 7 ! 🎄 Today we explore complete verilog design and testing of an inference chip in the TPU v1 architecture It's been a great week learning theory & implementation w @Alan_Ma_ !
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Hahaha, Never deleting this app... Where am I going to find this level of entertainment. 3000 lines of Verilog code my ass. Here is just the line count for HBM4 rtl, no test assets included:
The Anthropic TPU deal solidifies it. There's two companies that can make training chips, NVIDIA and Google. Elon tried with Dojo. Amazon tried with Trainium. DeepSeek tried with Huawei. Countless startups are flailing with multiple tapeouts and no real adoption. The funny thing
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update time on Cursor for DSP & Numerical Computing we have shifted from MATLAB to System Verilog and VHDL ( cause well we spoke to a lot of interested users and they liked the idea of having something similar for SV) inline chat completions works error selection and context
we are building Cursor for DSP & numerical computing. version 0.1 demo is here rough edges, but it works. we are shipping fast and pushing toward a better way to do science-based computing. actively looking for pre-seed partners who get the vision. tag investors, angels, or
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🏝️ Isle #FPGA Computer now has a Verilog 2D graphics engine. Blog: https://t.co/mYUWNGQuQ7 Code: https://t.co/jOTLD5nBGx
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Glimpses of IEP on RTL Design and verification using Verilog organised by NIELIT Aurangabad and inaugurated by Dr. Madan Mohan Tripathi DG and Honourable Vice Chancellor of NDU
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for anyone who wants to go beyond software and actually touch hardware logic. > this book gives beginners a direct path into digital design, Verilog, and VHDL; > the real tools behind chips, robotics, and high-speed systems
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Shrike edition - Keep Counting! > Soldered pmod, got the verilog working. > Happy go lucky, no negative slack. > Sweet 100 seconds of your life, over and over again. This was a small design, using 9 GPIOs and 159 of the 1120 available 6-input LUTs. Imagine the possibilities.
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