8,531 / 16,150 test cases now pass on the 8086 CPU — over half of the instruction set implemented. The design is shaping up nicely, and it’s still only about 1,200 lines of Verilog so far. 😄

finally got this FPGA delivered, now going to try synthesize our Verilog LLM implementation into this chip the idea is to avoid redundancy of generic cpu/gpu and synthesize LLM directly into silicon to achieve better performance it works in simulation, and if it works on this

Unwrapping TPUs 🎄: Day 14 x 14.5 - We close the loop on our verilog implementation from last week w full forward pass! - We emailed Cliff Young (one of the original TPU architects) with some questions .. and he generously wrote back !

MSX3の方針メモ MSX3の開発は、MSX2＋＋などの開発で遅れていますが、MSX2＋＋などで作成したVDPやSoundチップのVerilogを使うことを前提に、順番に進めることにしています

Unwrapping TPUs: Day 4 🎄 Proof of concept inference chip We implemented a tiny tiny TPU with super minimal verilog (hardcoded weights and activations). It was hype though

Doing verilog HDL 🙂

NVIDIA releases an open-source Deep Learning Inference chip design (based on Xavier), with full verilog source: https://t.co/SxnBWIl6qk

Unwrapping TPUs Day 7 ! 🎄 Today we explore complete verilog design and testing of an inference chip in the TPU v1 architecture It's been a great week learning theory & implementation w @Alan_Ma_ !

I spent a couple of weeks making a Verilog module for the 65C02 CPU. I needed it for Caliber 50 after painfully discovering that the 6502 (used in other cores) was not compatible with the more modern 65C02. I tested the new cycle accurate module on the Renegade core. So far, so

building Gateflow -Cursor for System Verilog updates UI improvements Waveform viewer version 0.1 ( still ass imo) this waveform viewer was a pain in the ass to build but a new version is already on the way. current issues need to be resolved where the waveforms are not

Dreaming up a CPU is easy. Verifying it actually works is the nightmare. During my time at Google working on TPU projects, I learned that you don't just "write Verilog." You have to build a complete ecosystem. I’ve built a custom CPU from scratch. Here is how I test it using

update time on Cursor for DSP & Numerical Computing we have shifted from MATLAB to System Verilog and VHDL ( cause well we spoke to a lot of interested users and they liked the idea of having something similar for SV) inline chat completions works error selection and context

Testing for side-channel attacks? 😎 GTKWaveViewer is a simple tool to help you visualize both analog and digital data logs, including Verilog VCD/EVCD files! 🤠 Check it out! 👇 https://t.co/3grySYaol4

Glimpses of IEP on RTL Design and verification using Verilog organised by NIELIT Aurangabad and inaugurated by Dr. Madan Mohan Tripathi DG and Honourable Vice Chancellor of NDU

Feel like Flash/Verilog system models? Then here… just crazy f***ing stuff. https://t.co/O1ch5lrCtb KianV for fuckers!

Unwrapping TPUs Day 4 —> we made a tiny tiny tiny TPU . Today we implemented a 2x2 Systolic Array from scratch in RTL! Enter the Verilog beast :O

Shrike edition - Keep Counting! > Soldered pmod, got the verilog working. > Happy go lucky, no negative slack. > Sweet 100 seconds of your life, over and over again. This was a small design, using 9 GPIOs and 159 of the 1120 available 6-input LUTs. Imagine the possibilities.

Unwrapping TPUs Day 5: 1. How do activations and weights*actually* stagger into a systolic array? We implement this in verilog in a scalable way :) 2. Theory for quantization (partial sums, 32-bit accumulator --> activation --> systolic array)

Thanks @ethereum foundation / @tkstanczak and @VitalikButerin for recognizing our work & effort! Ever since I hold ETH / started to program solidity / from a team of 4 building @verilog_audit the boutique auditing firm to building the next gen AI infra, have been dreaming about