OpenFASoC 2020-10 test chip on Global Foundries 12nm (GF12LP) process. Looking for more GF12LP test chips to tear down for a research project, please DM if you have something!

[Uni. Michigan] Using AI to design circuits: Prof. Saligane has been a leader in the development of OpenFASoC, along with a team of researchers external to the Uni. Michigan, Google .

Our internal design advisor @SaliganeMehdi and his team @UMichECE taped out an #OpenTitan style SoC w/#OpenROAD including automated Analog/MixedSignal blocks from OpenFASoC in both #Globalfoundries 12LP + #Skywater 130. 1st tapeout in an advanced finFET node: 350MHz signoff Fmax!

Visited the @Google booth at @risc_v days in #Tokyo2022Autumn today. Pretty Cool Setup by @proppy! Microscope visualizing MPW-I temperature sensor chips taped out using #OpenFASOC next to the GDS view :)

#OpenFASOC have recently released #cryogenic test structures that we hope @NIST will be using on #sky130_mpw -5. The generator is using all @SkyWaterFoundry 130nm open-source standard cells flavors and uses @OpenROAD_EDA tooling capabilities!

Applications for #GSOC2023 contributors start today! Work with us on projects involving @OpenROAD_EDA, #Verilog, #OpenFASOC, @f4pga toolchain & more to help us advance #opensource #hardware, #ASIC & #FPGA design: @GoogleOSS @mithro @antmicro @SaliganeMehdi

During #GSOC2023, you can also help us expand the potential of #OpenFASOC by adding support for #FEOL classes in @OpenROAD_EDA and creating a GDS writer. Interested? Submit your proposal: @GoogleOSS #Linux @SaliganeMehdi

Another project idea for @Google Summer of Code is simplifying and automating the #Verilog generation step in #OpenFASoC. Sign up and use your #Python & #cpp skills to help push #ASIC design forward:. .@GoogleOSS #GSoC2023 @SaliganeMehdi

Enhance performance and efficiency in #opensource #SoC design by joining us during @Google Summer of Code 2023. Help us create a special router feature in @OpenROAD_EDA and improve #OpenFASoC generators: @GoogleOSS #GSoC2023 @SaliganeMehdi

Explore the importance of building confidence in #opensource #EDA & #IC design using #OpenFASOC with @UMich's @SaliganeMehdi in his hybrid talk later today. Register for free: @OpenROAD_EDA @GlobalFoundries @linuxfoundation

For the sake of more #reproducibilityinhardware and #transparency I am trying to wirebond a good number of my #sky130_mpw -1 chips and/or ship them to the ones interested in replicating our testing: The goal is to compare results!

Invitation to Join Our Free Webinar on OpenFASoC and ALIGN for Chip Core Generation, by VSD Intern. VSD interns are performing exceptionally well. We are pleased to invite you to a free webinar where we will be discussing the innovative use of OpenFASoC…

[ Automated SoC, Mixed-Signal Design using OpenROAD and OpenFASoC. #RTL #GDSII #OpenSource #semi

Ali Hammoud, a Computer Engineering undergrad, has won the inaugural international Code-a-Chip competition. His project is based on the open-source hardware design tool called OpenFASoC. His faculty advisor on the project was Dr. @SaliganeMehdi .

Checkout: Github:

@matthewvenn @maxiborga Check out OpenFASoC for a whole bunch of similar analog designs -

If you're interested in this, you should also check out Mehdi Saligane's work with OpenFASOC.

@matthewvenn @Kitten_Tech @hackaday Take a look at the OpenFASoC project - and

@bvernoux @suarezvictor @hansfbaier @WCH_TECH @SaliganeMehdi @SaliganeMehdi is always looking for new students and collaborators at other universities to help contribute to OpenFASoC -

#2022 Goals: Improve overall PPA and add more Analog/MixedSignal blocks and cool hardware security features using #OpenROAD and #OpenFASOC!.