RISCVchip Profile Banner
RISC-V.chip.haus Profile
RISC-V.chip.haus

@RISCVchip

Followers
880
Following
992
Media
171
Statuses
602

News and information about the RISC-V instruction set architecture and its implementations, brought to you by @ChipHaus.

Joined January 2019
Don't wanna be here? Send us removal request.
@RISCVchip
RISC-V.chip.haus
@RISCVchip
4 years
RT @linuxdevices: SiFive RISC-V Rack Cluster and custom PC power up with HiFive Unmatched: SiFive and AB Open demoed a “SiFive RISC-V Rack….
0
2
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
4 years
RT @TheRegister: Chatter around GPUs for RISC-V is growing
0
7
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
4 years
“RISC-V Business: Testing Gaming and More on the HiFive Unmatched from @SiFive” (@Level1Techs, 14 min.).📺
0
1
3
@RISCVchip
RISC-V.chip.haus
@RISCVchip
4 years
RT @MouserElec: Register for a LIVE panel discussion with @MicrochipTech and @crowd_supply exploring the future of RISC-V this Tuesday!. De….
0
3
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @MisterTechBlog: #Mynewt #RISCV is Hardcoded for SiFive FE310 . Here's our fix for #PineCone #BL602 @ThePine64. .
0
4
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @BrunoLevy01: #femtorv32 #riscv core for #FPGA: implemented basic ELF support. I'm using it at two different places:.* in femtOS, that c….
0
5
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @BrunoLevy01: #femtorv #riscv core for #fpga: added a tutorial for the ECP5 evaluation board.Coming next: the FO….
0
1
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @dev_msyksphinz: "Hardware description language Chisel & Diplomacy Deeper Dive" my presentation video in RISC-V Study meetup online Dec.….
0
2
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @ogawa_tter: =>."MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect", @LucaBeniniZhFe , to appear at DATE21 (….
0
3
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @ogawa_tter: @LucaBeniniZhFe @pulp_platform =>."A Tiny #RISCV Floating-Point Unit", L. Bertaccini, ETH Zurich, RISC-V Summt 2020, Dec 8….
0
1
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @ogawa_tter: =>."MEEP's emulated accelerator architecture", Nov 15, 2020 VAS Accelerator Tile.Shared L2: 4 MB.Co….
0
3
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
Project Oberon 2013 on RISC-V.🛠 💬 Cf.
0
0
1
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @ogawa_tter: =>.RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture, RISC-V Global Forum, Spe 3, 2020.09:58 https….
0
2
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
“What is a system-on-chip (SoC), and why do we care if they are open source?” (@BunnieStudios, 2020-11-10).👉 💬 💬
0
1
3
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @Hacksterio: .@SipeedIO plans $12.50 Linux-capable RISC-V dev board family based on the XuanTie C906: https://t.….
0
1
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @pulp_platform: As the #RISC-V summit is approaching, this week we would like to introduce PULP's speakers. On Tuesday, 8 December 2020….
0
2
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @ABOpenLtd: A Look at the RISC-V PC from SiFive. #RISCV #FOSSi
Tweet media one
0
10
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
RT @TechCrunch: SiFive’s new PC is bringing open-source computing closer to reality by @dannycrichton.
0
16
0
@RISCVchip
RISC-V.chip.haus
@RISCVchip
5 years
“A Plan 9 C Compiler for RISC-V RV32GC and RV64GC” (Richard Miller, 2020-10-19, 33 min.).📺
0
6
8