luke k.c. leighton
@lkcl
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Ethical Libre Software Developer and Advocate Eco-conscious Libre Hardware Designer lkcl@fizzy:~/src/libresoc/soc$ ps auxww | grep "vi " | wc 1510
The World. (Planet Earth)
Joined March 2009
My newsletter has one subscriber. Me. Help me change that over on LinkedIn. Week 1 includes #AI, #biotech, #cleantech, #spacetech, and #semiconductors. Plus a touch of #SciFi.
linkedin.com
Making and marketing the future.
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https://t.co/vxavSvm9mv OSSYM2023 at @CERN 5th International Symposium on Open Search deadline is 31st May
indico.cern.ch
4 - 6 October 2023 The #ossym Open Search Symposium series brings together the Open Internet Search community in Europe for the fifth time this year. The interactive conference provides a forum to...
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it took me a while to notice that ARM has special instructions for linked-list-pointer-chasing https://t.co/8Ieio1kyNU however i am delighted to confirm that SVP64 Vector instructions for linked-list-chasing works. @OpenPOWERorg
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This is important work! Help ensure it continues by becoming a @BlockchainComns sponsor. [13/13]
github.com
Blockchain Commons is a "not-for-profit" social benefit corporation committed to open source , advocating for the creation of open, interoperable, secure & compassionate digital infra...
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This week’s Silicon Salon 4 explored the challenges and offered some insights into solutions at the intersection of cryptography and semiconductor manufacturing. Explore the presentations by Andrew Poelstra, Red Semiconductor, and @cramiumlabs now! [1/13]
siliconsalon.info
The Silicon Salon brings together the semiconductor and cryptography communities to talk about the future of semiconductor design that can support crypto.
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Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5].
Most RISC ISA chip designs are missing instructions allowing for chaining to create vector results for biginteger operation used in cryptography. @lkct & David Calderwood will be talking on this topic at Silicon Salon 4, hosted by @BlockchainComns. 🧵[1/9]
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doing the write-up for OPF ISA WG External RFC ls016 - Integer Twin-Butterfly DCT/FFT "mul-add-sub-shift-imm" https://t.co/QB7UFwWuqg the number of instructions it replaces is *eight*. and it's in-place. no temp regs. massive savings. @IBMResearch @OpenPOWERorg @GanesanBlue
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with many thanks to @NgiSearch and @FundingBox we will be optimising the SVP64 Draft ISA (proposed to the @OpenPOWERorg ISA WG last week) for Search. VectorCamp will be porting VectorScan to SVP64, Vantosh optimising libc6 string/memory routines
linkedin.com
RED Semiconductor secures grant funding to showcase the power and performance efficiency of its Vantage microprocessor architecture in Internet Search Algorithms. RED Semiconductor, in collaboration...
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SVP64 has now been formally submitted in full to the @OpenPOWERorg Foundation's ISA TWG. Comprising some 150+ pages it needed splitting into five RFCs: ls001 PO9, ls005 XLEN, ls008 setvl/svstep, ls009 SVP64 and ls010 REMAP.
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i am delighted to be able to announce that i am the OpenPOWER Foundation representative as a Voting Member of the Power ISA Working Group for RED Semiconductor Ltd. hugely grateful to @IBM @OpenPOWERorg and to @NLnetFDN
linkedin.com
Luke Leighton, RED Semiconductor Limited founder, becomes a voting member of the OpenPOWER Foundation Instruction Set Architecture Technical Working Group RED Semiconductor is pleased to announce...
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anyone any thoughts on whether LD/ST-Index-Shifted should be added to Power ISA? it would be *37* new instructions(!) of the form "EA = RA + (RB<<shift)" where "shift" would, just like has been in ARM and x86 for decades, a value 1 thru 4.
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@NLnetFDN @OpenPOWERorg first revision of ls012 is now in https://t.co/kq4RclN4gd and version v4 of ls001 is also in https://t.co/Orc6TJdLic - ls001 contains the Formal request for PO9 to be allocated 50% to SVP64 and 50% for any other (future) 64-bit instructions.
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@NLnetFDN @OpenPOWERorg more details here - it's the biggest proposed upgrade to the Power ISA since Motorola VLE-Book, adding a 24-option TBM-style instruction called `bmask` for example.
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i'm writing up OpenPOWER ISA Working Group External RFCs full-time at the moment, to be proposed for the SFFS subset. right now i'm doing a "summary" document of future Draft Scalar instructions. feedback welcomed. thx to @NLnetFDN @OpenPOWERorg
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> Meanwhile, the processor's stream performance with eight channels of DDR4-3200 memory crosses the 50GB mark. Wow! /he exclaimed, while reading this article on an tablet-grade arm SoC doing 65GB/s of RAM BW https://t.co/umVv8xEMyS
tomshardware.com
The 3D5000 has come out of the oven.
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@jon_trossbach @geofflangdale the only other ISAs i know of that have this type of "large" carry (more than 1 bit carry-in/out) are Mitch Alsup's MyISA 66,000 and a really *really* early version of Power ISA (Power ISA 1 or so!) they had a 32-bit Carry-In/Out SPR, later dropped unfortunately. know any others?
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nutshell: we're proposing 3-in 2-out mul/div/shift ops that use one extra 64-bit reg as "carry-in carry-out". SVP64 "magically" chains them. operand fwd bus drops them down to 2-in 1-out (except 1st and last in chain). @jon_trossbach @geofflangdale
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thx christopher for the opportunity. i'd like to have also presented about the Vectorised chacha20 algorithm we did (all 20 rounds in 10 in-register parallel vector instructions, i.e. a single L1 Cache Line) but settled instead on biginteger operations.
Our next monthly call will coincide with Silicon Salon 4, with topics such key exfiltration prevention w/ @Blockstream's Andrew Poelstra, bigint in silicon w/ @lkcl, and discussion on open hardware requirements. https://t.co/UoFZwh0Een [10/12]
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Mathematics, programming, the universe. The eternal uncoiling. By Matthew Hughes, @tasty_plots, https://t.co/fhbyhDMimd, Used with permission.
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