CHIPSAlliance
@CHIPSAlliance
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CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
Joined February 2019
The whitepaper is here! Designed to demystify the current state of #openhardware #opensilicon, outline the challenges ahead, and chart a path forward for everyone from startups to silicon giants.
chipsalliance.org
CHIPS Alliance has just released a new white paper, CHIPS Alliance and the Open Hardware Landscape, designed to demystify the current state of open hardware, outline the challenges ahead, and chart a...
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The first-ever CHIPS Alliance newsletter is live! Check it out for the latest community updates. 👍 Like if you're building open source silicon.🔁 Share to connect more developers to the ecosystem.💬 Drop a comment if you have updates or news to share .
linkedin.com
Your quarterly roundup of technical updates, events, and community highlights. Welcome to the new CHIPS Alliance Newsletter.
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What does a collaborative open source chip design environment look like?. At DAC, CHIPS Alliance’s Robert Mains moderates a session on open ISAs, PDKs, EDA, cloud-based design, & Caliptra. 📅 June 25 | ⏰ 10:30am.🔗 #DAC2025 #CHIPSAlliance #OpenHardware
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What does a collaborative open source chip design environment look like?. At DAC, CHIPS Alliance’s Robert Mains moderates a session on open ISAs, PDKs, EDA, cloud-based design, & Caliptra. 📅 June 25 | ⏰ 10:30am.🔗 #DAC2025 #CHIPSAlliance #OpenHardware
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New Blog: Interactive #RTL Coverage Dashboards for #VeeR and #Caliptra. In this post, @antmicro walks through how Coverview is used to track verification for the VeeR EL2 core, part of the Caliptra project.
chipsalliance.org
Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for execut...
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RT @antmicro: New revision of Antmicro's highly popular Open Source Jetson Orin Baseboard is back in stock at @CircuitHub. Same small footp….
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Come check out the #Caliptra Root of Trust demo booth A13 courtesy of #AMI at @OpenComputePrj EMEA Summit #Dublin.
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Heading to the @OpenComputePrj 2025 EMEA Summit? Don’t miss this talk. Caliptra – Subsystem Firmware Stack.Wednesday, April 30 · 9:50 AM.Level 1 - Liffey Hall 2. #Caliptra #OCP2025 #CHIPSAlliance #OpenSourceSilicon #FirmwareSecurity
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Heading to @OpenComputePrj #OCPEMEA next week?. 🔹 Meet CHIPS Alliance ED Rob Mains at Booth A13.🔹 Catch Caliptra firmware stack talk – April 30, . 09:50, Liffey Hall 2.🔹 Explore open source silicon + system design with us!. #Caliptra #OpenCompute #OpenSourceSilicon
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Topwrap is an open source toolkit for creating machine- and human-readable top level designs, w/ reusable user-defined repositories, automatic interconnect generation & an enhanced interface grouping mechanism: @antmicro @risc_v @linuxfoundation.
chipsalliance.org
ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. Taking advantage of this modularity and enabling automation and reuse of blocks across designs requires...
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Read about @antmicro's further developments towards Caliptra 2.0 RoT: support for the @risc_v VeeR EL2 core w/ User mode and PMP in the embedded Tock OS: @talkingtock @AMD @Google @Microsoft @nvidia.
chipsalliance.org
The Caliptra Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the CHIPS Alliance, is steadily heading towards its 2.0 release – an effort Antmicro is actively...
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RT @antmicro: Meet us at #RISCVSummit this week to learn about @risc_v and @CHIPSAlliance collaboration and the synergies offered by the op….
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The interplay between hardware and software is a critical part of designing next-gen chips for e.g. AI and HPC. Join @CHIPSAlliance, @OpenPOWERorg and @RISC_V at this co-located #OSSummit event for industry insight on the current open source landscape.
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RT @antmicro: At #OSSummit Vienna, we will be giving a talk on @CHIPSAlliance #Caliptra 2.0 led by @AMD @Google @Microsoft @NVIDIA. We will….
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The interplay between hardware and software is a critical part of designing next-gen chips for e.g. AI and HPC. Join @CHIPSAlliance, @OpenPOWERorg and @RISC_V at this co-located #OSSummit event for industry insight on the current open source landscape.
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CHIPS Alliance is a mentor organization at this year's @Google Summer of Code! Join our mission to push forward #opensource #hardware, #ASIC & #FPGA design. Check out our project ideas & apply by April 2: @GoogleOSS @antmicro @risc_v @f4pga @OpenROAD_EDA
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This year at #OSSummit in Seattle, @risc_v, @OpenPOWERorg and @CHIPSAlliance are teaming up for a mini summit! Join us on April 15 to hear from speakers from @Microsoft, @intel, @awscloud, @antmicro, @RedHat, @Codasip, @uoregon and @linuxfoundation:
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As #Rowhammer continues to be a serious threat for DRAM technologies, @antmicro released a SO-DIMM (LP)DDR5 testing platform with PCIe, adding to the #opensource FPGA-based testing suite developed for @Google. Learn more: @AMDembedded.
chipsalliance.org
Ten years after the first disclosure of the initial Rowhammer security exploit, new DRAM vulnerabilities continue to be discovered, and developing new and efficient mitigation techniques requires a...
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Get more insight to verilation processes and ASTs with astsee, @antmicro's #opensource toolkit for pretty-printing, diffing, and exploring ASTs from a wide range of sources including #Verilator. Learn more: #fpga #asic #json.
chipsalliance.org
Among other things, Antmicro’s work towards improving the vertical integration potential of customers designing ASIC solutions often sees them enhance one of the flagship open source projects in this...
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RT @antmicro: In space no one can hear your hardware beep. See how simulation in @renodeio lets you scalably develop & test complex, hetero….
antmicro.com
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