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The BOOM Processor Profile
The BOOM Processor

@boom_cpu

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427

An open-source RISC-V out-of-order processor

Berkeley, CA
Joined January 2016
Don't wanna be here? Send us removal request.
@boom_cpu
The BOOM Processor
6 years
BOOM hits a new milestone! Read about the new v3, SonicBOOM! Slightly higher IPC in SPECint17 and Coremark relative to the A72s in AWS Gravitonv1! Appearing virtually at the next CARRV workshop, this Friday May 29th. ( https://t.co/iCeaninMnC). 💥
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@EsperantoTech
Esperanto Technologies
4 years
News flash: Esperanto Technologies Partners with Intel to Advance Massively Parallel RISC-V-based AI Acceleration Solutions! #Intel #riscv #AI #ML #semiconductors @esperantotech @risc_v https://t.co/CDadsZ4NU4
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@kasanovic
Krste Asanovic
4 years
Intel, welcome to the @risc_v Revolution!
@Calista_Redmond
Calista Redmond
4 years
Today @Intel declares their support for RISC-V, further igniting cultivation of opportunity and collaboration across industries. Together we have the power to change the course of history. Welcome Intel as a premier board member of @RISC_V! https://t.co/1k0W3vfzhw
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@sbeamer
scott beamer (@[email protected])
4 years
Currently enjoying teaching Agile Hardware Design, and we are happy to open-source all of our materials & lecture recordings:
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@boom_cpu
The BOOM Processor
4 years
VLC just added some patches to support the recently minted RISC-V Vector spec! Super cool! (via https://t.co/M6WgtTbHOg)
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reddit.com
Explore this post and more from the RISCV community
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@EsperantoTech
Esperanto Technologies
5 years
Hotchips 2021 advance program online now! @hotchipsorg Hear @EsperantoTech Chairman and Founder Dave Ditzel @DaveDitzel speak on "Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip" August 24.
hotchips.org
A Symposium on High Performance Chips
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@boom_cpu
The BOOM Processor
5 years
Pretty neat to see this stuff listed on wikichip, although it is a little Spartan at the moment. 🤔 T0 and Rocket especially deserve more attention.
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en.wikichip.org
University of California, Berkeley is a public research university. UC Berkeley is the flagship institution of the ten research universities that are part of University of California system, located...
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@boom_cpu
The BOOM Processor
5 years
Super exciting news: "Esperanto Technologies to Reveal Chip with 1000+ Cores at RISC-V Summit!" (spoiler alert: I (Chris) worked on ET-Maxion, which is BOOM-derived💥!) @EsperantoTech https://t.co/xw7Tn9lurK
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@sbeamer
scott beamer (@[email protected])
5 years
Getting the traditional #HotChips2020 experience with a hot California summer and an ice cream bar for final break :)
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@wallento
wallento
5 years
I have been elected to represent individuals and the community on the @risc_v Board of Directors. Get in touch if you have any topics you want to get addressed! Looking forward to be your voice on the board and this exciting role 🥰
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@kenshirriff
Ken Shirriff
6 years
I reverse-engineered the register file in the Intel 8086 microprocessor. Each register cell is static, based on two inverters in a loop. Some registers are multi-ported, more complexity than I expected in a 42-year-old processor. https://t.co/qDxgIhtnXQ
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@boom_cpu
The BOOM Processor
6 years
Of course, we don't just do the occasional code-drop; if you want bleeding edge changes, you can always see the latest commits at ( https://t.co/u0sIpSYInt). Caveat Emptor, of course. =)
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github.com
SonicBOOM: The Berkeley Out-of-Order Machine. Contribute to riscv-boom/riscv-boom development by creating an account on GitHub.
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@boom_cpu
The BOOM Processor
6 years
Many of you have been asking us for the source code to SonicBOOM! We can now officially point you to the BOOMv3 GitHub release (concurrent with Chipyard v1.3). Get the links and read the change log at:
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@boom_cpu
The BOOM Processor
6 years
Incremental compile for HW simulations & synthesis!! But now how am I suppose to schedule my coffee breaks?
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@boom_cpu
The BOOM Processor
6 years
New SonicBOOM features include auto-predication of short forward branches, a multi-load load/store unit, a TAGE-L (loop) predictor, RVC compressed support, RoCC co-processor support, and a FireSim/FPGA+Dromajo ISA model checker for verification (Fromajo 🧀)!
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@kasanovic
Krste Asanovic
6 years
Happy Birthday, @risc_v ! 10 years old today! What an incredible first decade it's been - thanks to the whole community for bringing us along this far: https://t.co/oSBGFrPfdA
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