Adam Greig
@adamgreig
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🚀; also electronics, RF, signal processing & comms, embedded and scientific software, FPGAs, Rust. He/him. 🦋 @agg.io
Oxford, UK
Joined July 2008
📣 Hello all! The 2024 Embedded WG Survey is now live! https://t.co/JKJ8brn7KJ We'd like to hear about your use of Rust on Embedded Systems, and you can help us by taking this anonymous survey, run by the Rust Survey team. CC @rustlang - and all other RTs/shares appreciated!
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📣 Heads up! `embedded-hal` has released 1.0.0-rc1! This release candidate is intended to be the "last check" before the 1.0.0 version is finalized. If you maintain a HAL that impls e-h traits, or a driver that uses them, please test it ASAP! https://t.co/TG30KOOLqa
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While I still numerologically hope Twitter makes it to July so it's a round 15 years since I signed up, if you're sensibly setting up alternatives you can also find me at @adamgreig@mastodon.social or https://t.co/ojHKwMtniM.
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and, it turns out loading a bitstream to SRAM that has an SPI_MODE command causes an abort if the SPI flash doesn't already contain a valid bitstream (??), so ecpdap will now also remove those commands when loading to SRAM. works with any cmsis-dap probe, give it a try!
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ecpdap (ECP5 FPGA programmer, https://t.co/hUUUIxflQx) 0.2 now out, with live patching bitstreams to fix compatible IDCODEs, which is great when stock shortages means you have a whole mix of compatible ECP5s and don't want to manage a ton of bitstream variants!
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It's time for "This Year in Embedded Rust: 2021"! Special thanks to @therealjpster for putting this together, along with the countless contributors to the ecosystem over this year! Here's looking forward to another wonderful year of #embedded @rustlang! https://t.co/JIMMk3sUiW
blog.rust-embedded.org
As 2021 draws to a close, we thought we'd take a look back at what's happened over the last year in Embedded Rust, both within the working group and in the larger community.
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(1.51 is beta.4, 1.52 is nightly-2021-04-03, numbers are wall clock time of a single run on my desktop, this isn't a super scientific study or anything!)
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Of course, these are all clean builds from scratch - most builds will be much quicker since the PACs don't need rebuilding, which is probably why I hadn't noticed before. Still, getting a clean build from 1min down to 20s is pretty amazing!
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The dramatic drop in 1.47 corresponds with LLVM11, which no doubt also deserves some credit here, but even if we look at just the underlying PACs the improvement release-on-release has brought the large stm32h7 crate down almost half!
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this is a minimal demo executable that just blinks an LED using a timer, but it has to build the PAC crate (the register abstraction layer) stm32f4, which used to absolutely dominate build times; over the last year the build time has dropped by **67%**!
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A few weeks ago someone on the embedded Rust chat commented that their build times seemed to have gotten better, and sure, each release brings some nice gains, but I hadn't noticed just how dramatic some of the improvements have been...
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The CMSIS-DAP/JTAG stuff is from jtagdap (shared with ecpdap), and the SPI flash stuff is from spi-flash-rs (also shared with ecpdap), so spidap's implementation is barely 20 lines of "how to express SPI in JTAG":
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I've just released spidap, a followup to ecpdap, which allows accessing SPI flash directly from a CMSIS-DAP probe in JTAG mode (JTAG looks like SPI if you squint), handy for iCE40 boards (and anything else with SPI flash...)
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Want to measure time down to ~50 picoseconds on an ECP5 FPGA using nmigen & open source tools? I got you: https://t.co/v2Q79VRG1u (Spent a long time figuring out the placement and routing for this when building an ADC a while back, too cool not to share)
gist.github.com
ECP5 Delay Line with ~50ps precision. GitHub Gist: instantly share code, notes, and snippets.
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(quickly hacked-together script at https://t.co/j8cnIE8hFC)
gist.github.com
GitHub Gist: instantly share code, notes, and snippets.
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finally got around to automating "hmm, it only *just* failed timing, what if I try 20 more seeds in nextpnr, one after the other, by hand?"
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I've been slowly prodding ECP5 DSP unit support in Trellis/nextpnr/Yosys and it can now synthesise a working multiply-accumulate (MAC), but there's a lot still to figure out... with the aid of this colourful new diff tool!
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Getting Started with ECP5 FPGAs on the Colorlight i5 FPGA Development Board https://t.co/bIRGtu5c2W
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If you've got some ECP5 boards and CMSIS-DAP probes lying around, I'd love feedback if you'd like to try it out; there are pre-built binaries for x86_64 Linux/Windows on GitHub or you can `cargo install ecpdap`
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