Kicking around an idea for a sub-$100 PCIe dev board. Affordable FPGA + PCIe x2 endpoint + x2 root complex over OCuLink, USB3 debug, PMODs. Plug into a PC, RPi, or another FPGA for driver dev, PCIe experiments, emulation, and snooping. Would you use this? How?

Check out the latest update from the Altera Innovation Lab at Crowd Supply to learn more about workshop source-code release and other project updates. https://t.co/qIN3YfhWW1

Weekend FPGA side quest is ready. Got a DualShock controller working with an RP2040 + FPGA, and it now outputs a little hardware GUI over HDMI. More info in today's livestream → https://t.co/qoJg4tq51Y

Trying out some Oculink Adapters for the Framework computer! Going to test with some FPGA boards.

A Deep Dive into Using PIO and DMA on the RP2350

Kyle_Tuck in the Framework community built one of the most requested modules for Framework Laptop 16: an Oculink adapter!

Weekend FPGA side quest! Gonna get Altera Nios-V talking to the AD9364 over SPI and fire up the LVDS test modes. https://t.co/gGzasH9hQ5

Got simple Vitis HLS blocks working with the MicroBlaze RISC-V processor using the AXI4-Stream FSL features. Thinking about trying some Advent of Code 2024 puzzles as fun accelerator challenges next!

Here is the CoreScore for AMD’s Spartan UltraScale+ on the SCU35 dev board ⇒ 83 SERV RISC-V cores! Awesome, easy-to-use benchmark from @OlofKindgren . I’ll have the basic PR up soon.

This is a great video on all the fun behind designing a soft RISC-V processor from scratch.

You mean I can get this working on AMD ZYNQ & Versal FPGAs?

Weekend project: Using the MicroBlaze V RISC-V AXI-Stream, I want to try talking to the PIOs on the RP2040. Going to prototype the link and see what kind of speed I can get. Feel free to drop by! https://t.co/PKdwByvUd1

The AMD MicroBlaze V (RISC-V) can handle AXI-Stream packets with dedicated instructions. The soft processor can do register direct to an FPGA accelerator. Gonna try a few simple HLS accelerators and see how well it works.

This is a big cable mess but got the White Rabbit (nanosecond-level time synchronization) sorta working! I’m using two baseboards, one with an Acorn acting as a clock reference and the other with a Litex M2SDR acting as a client. I’m using a direct attach cable instead of a

Weekend FPGA project time! Exploring the Altera Agilex 5 PCIe PIO example using a Python driver and a Raspberry Pi CM4 host. Drop by the stream and hang out! https://t.co/S0LvLYmM8E

My next Altera FPGA AI video will show how to make simple ONNX models to test the FPGA AI Suite streaming interfaces on the Agilex 5, checking control and data flow before running a full neural network. https://t.co/utFB9UyG4J

Its amazing how fast a little RP2040 can go! With a Parrallel bus of 8 bits you can easily support 40 MB/s bus to the AMD FPGA. Can you use a RP2040 to do a SMI-like memory interface to the co-FPGA?

@ATaylorFPGA

I got a FPGA board from @ATaylorFPGA and wanted to play around with high-speed IO from the RP2040 to the AMD Spartan 7 FPGA. Hopefully the new https://t.co/JO9RlQyygC setup simplifies multi-streaming! https://t.co/5O6Ycmr2IF

I modified the official Altera Docker image to include xRDP, RISCFREE tools, and a ready-to-build setup for the Agilex 5 FPGA DisplayPort example. Added easy build instructions so anyone can follow along with tomorrow’s livestream. https://t.co/Fo72acBcVP