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Our work on page walk side channels was accepted at @IEEESP 2025 (#ieeesp2025)! The full paper is now available at: https://t.co/15cICFDfpn and our code is available at: https://t.co/cz5j6JPRYb

Join us at #usesec22 at 5pm to learn about how to mount microarchitectural attacks on large server processors *even when known attack vectors inside the cores and caches are closed*, and to gain useful, new insights on how to mitigate these attacks *without hardware changes*!

For more information visit our website ( https://t.co/ovH1hWk0iq), read our paper ( https://t.co/YlvelXk0Su), and come see @YingchenWang96’s and my talk at @USENIXSecurity 2022 (#usesec22)!

The takeaway is that current cryptographic engineering practices for how to write constant-time code are no longer sufficient to guarantee constant time execution of software on modern, variable-frequency processors.

We then show that Hertzbleed is a real threat to the security of cryptographic software, by describing a novel chosen-ciphertext attack against SIKE. The attack allows full key extraction via *remote timing*, despite SIKE being implemented as “constant time”.

In our paper, we reverse engineer a leakage model for the frequency side channel. Our carefully designed experiments show, for the first time, that the HD and HW of data *individually and non-uniformly* contribute to power consumption and frequency on modern x86 CPUs.

Making matters worse, data-dependent frequency differences directly translate to execution time differences (as 1 hertz = 1 cycle/second). This means that the same program can take a different wall time to compute, for example, 2022 + 23823 compared to 2022 + 24436.

We found that, under certain circumstances, dynamic frequency scaling depends on the data being processed, enabling *frequency side channels*. The cause is that periodic frequency adjustments depend on the current CPU power consumption, which is data dependent.

Modern CPUs dynamically adjust their frequency to reduce power consumption (during low CPU loads) and ensure that the system stays below power and thermal limits (during high CPU loads). You might have heard of this feature under names like DVFS, Turbo Boost, Turbo Core, etc.

We found a way to mount *remote timing* attacks on *constant-time* cryptographic code running on modern x86 processors. How is that possible? With #hertzbleed! Here is how it works (with @YingchenWang96). https://t.co/SRUgBRQpu2

We found a way to defeat pointer authentication (and forge kernel pointers from userspace) on the Apple M1 via a new hardware attack. Here’s how it works- https://t.co/6Kz3jnRtwI

We found a way to leak data on Apple Silicon processors that is "at rest": that is, data the core never reads speculatively or non-speculatively. This will be an odd one, so stick around for the 🧵 and see

Researchers demonstrate first microarchitectural side-channel attacks that leverage contention on the CPU ring interconnect against #Intel CPUs, allowing malware to pilfer sensitive data from modern processors. Read details: https://t.co/6351baVPUu #infosec #tech #cybersecurity

Importantly, unlike prior attacks, our attacks do *not* rely on sharing memory, cache sets, core-private resources or any specific uncore structures. As a consequence, they are hard to mitigate using existing "domain isolation" techniques.

Finally, we show two examples of side channel attacks that exploit ring contention. The first attack leaks key bits from vulnerable EdDSA and RSA implementations. The second attack infers the precise timing of keystrokes typed by a victim user.

We show how the above conditions can be used to build a cross-core covert channel with a capacity of over 4 Mbps from a single thread, the largest to date for a cross-core covert channel that does not rely on shared memory.

We describe, for the first time, the necessary and sufficient conditions to create "ring contention". Such contention occurs when multiple agents contend on the ring interconnect and suffer small delays in their memory accesses.

In our paper, we reverse engineer the architecture of such ring interconnect. Read our paper to learn more than you ever thought you wanted to know about how the Intel CPU ring interconnect works, down to arbitration policies, protocols and physical implementation.

Context: Multicore CPUs have many components (agents) that communicate with each other. The ring interconnect is what many Intel CPUs use to move data between these components (e.g., during a memory access).