Processor .Microarchitecture. An Implementation Perspective. Antonio González

ALU-Centric Computer System Design (CPU).This processor microarchitecture reveals the essential building blocks that enable modern 𝐂𝐏𝐔𝐬 to execute program instructions efficiently. Read Whole Thread 🧵👇

THE MICROARCHITECTURE.OF PIPELINED AND.SUPERSCALAR.COMPUTERS. AMOS R. OMONDI

I started a newsletter! For my first post, I talk about Google's TPUs and how they compare to Nvidia's chips. I cover their microarchitecture, Google's data center supremacy and why, despite TPUs being great chips, everyone rushes to Nvidia anyway. Link in bio!

Researchers reverse engineered Nvidia Ampere microarchitecture, revealing how the issue logic works including the policy of the issue scheduler, the structure of the register file and its associated cache, and multiple features of the memory pipeline.

360 CPU cores go brrrr, coupled with 1.4 TB of RAM. Magnetron's CPU compute engine uses all threads to significatly improve training performance on this AMD Epyc server. Also then Zen4 microarchitecture is fully utilized by using AVX512 instructions, operating on 512-bits at the

The hallucinatory world of Ada Lovelace cultists continues to expand. NVIDIA has now even named a GPU "microarchitecture" after the old girl (GeForce RTX 40). She is described as a "19th century mathematician" (chortle) and less ambitiously as "one of the first programmers". We

It’s a #COMET! ☄️ .A half-finished meteor/comet #silicondoodle is placed on the top corner of this vintage IC made by #Digital (#DEC). COMET is a microprogrammable computer specifically designed to emulate the VAX-11 microarchitecture. VAX (Virtual Address eXtension) was invented

The Intel Pentium Pro CPU (Socket 8) was released on November 1, 1995. It was designed for high-end desktops and servers and introduced Intel's P6 microarchitecture, which later evolved into the Pentium II and III. Shown below in order, with the first 133Mhz Engineering Sample:

We're hosting a space at 9 PM IST to discuss GPU Microarchitecture and Graphics. Tune in you wanna make it in life.

🔔 Get a jump on awards season by putting your nominations in soon—here are deadlines coming in June:. 🏅 June 15: Rau (microarchitecture).🏅 June 30: Seymour Cray/Ken Kennedy/Sidney Fernbach (high performance computing). #tech #techawards #computerawards

Our paper @lucacolagrande3 "Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration" which extends Snitch & proposes a low-overhead optimized microarchitecture, has been accepted for #ISLPED2025. See

I highly recommend reading this fantastic interview with Zen daddy Mike Clark. He reiterates what my fellow microarchitecture nerds have known about the relationship between ISA and power consumption (hint: the internet overblows it).

microarchitecture is about taking magic rocks, and using light to inscribe magic symbols into them so that when using the proper incantations they do things. computers are occultic and i’m tired of acting like they’re not

I am chairing the second edition of the microarchitecture security conference (uASC'26). Paper deadline for the first cycle is July 15. Please spread the word, submit, and/or join us in charming Leuven in February 2026! More info:

AMD XDNA 🧠.This microarchitecture is notable for its ability to emulate key aspects of a biological neuron's functionality. It performs this emulation more effectively than NVIDIA's Tensor Cores on a per-unit basis, which contributes to its superior energy efficiency.

Explanation of branch and load delay slots in MIPS architecture, discussing their purpose, implementation, and the trade-offs involved. Source: Intro to Microarchitecture - Carnegie Mellon - Computer Architecture 2015 - Onur Mutlu

#GothicArchitecture Part of the impact of microarchitecture is its relationship to scale, as a person (and not a giant) most of us loom over the architectural features and thus it changes our relationship to the features depicted. 🧵.Ely; Rouen Cathedrals

What about the MIOC (Memory and IO Controller) aka MSBC (Memory System Bus Controller) microarchitecture of the #HP #PA 7000/7100/7150 chip-set?