Explore tweets tagged as #designverification
๐ Weโre hiring!. ๐ Open Positions:.1๏ธโฃ Design Verification Engineer (4-20 yrs) .2๏ธโฃ Physical Design Engineer (4-20 yrs) . ๐ Locations: Hyderabad & Bangalore .๐ฉ Send CV: careers@smartsocs.com . #Hiring #DesignVerification #PhysicalDesign #TechCareers #SmartSoC
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๐ค DVCon U.S. 2026 is looking for one standout panel to take the stageโsomething timely, relevant, and ready to spark real conversation in the #designverification space. Submit your proposal by November 2, 2025. ๐ Learn more and submit:
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๐ ๐ช๐ฒโ๐ฟ๐ฒ ๐๐ถ๐ฟ๐ถ๐ป๐ด | ๐๐ฒ๐๐ถ๐ด๐ป ๐ฉ๐ฒ๐ฟ๐ถ๐ณ๐ถ๐ฐ๐ฎ๐๐ถ๐ผ๐ป ๐๐ป๐ด๐ถ๐ป๐ฒ๐ฒ๐ฟ๐. Be part of a dynamic team shaping the future of semiconductors! ๐ก. ๐ฉ Apply now: careers@smartsocs.com. #DesignVerification #SV #UVM #PCIE #BangaloreJobs #HyderabadJobs #VLSICareers #SmartSoC
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Weโre Hiring โ Join Our VLSI Dream Team!. Weโre excited to announce a Mega Hiring Drive happening this weekend at Ignitarium Bangalore! If you're a #VLSI professional looking for your next big move, this is your moment. #VLSIHiring #MegaDrive #ChipDesign #DesignVerification
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VLSI design house . #vlsi.@VLSIRecords @VLSISystemDes .#physicaldesign.#desighnfortest.#designverification
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Formal verification can be complex, but our DV expert Athira Variar breaks it down in her #latestblog: Simplifying Formal Verification Debugging with Auto-Generated Testbenches. ๐ Read the full blog here: #FormalVerification #DesignVerification
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Boost Debugging Efficiency with X-Tracing in QuestaSim!. Email us at marketing.india@prolim.com to learn more!. #PROLIM #Siemens #XTracing #QuestaSim #DesignVerification #ASIC #FPGA #VLSI #UVM #Debugging #EDA
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Weโre hiring Design Verification Engineer!. ๐ Bangalore & Hyderabad. 7โ15 Yrs | PCIe | Ethernet | SV | UVM. Join SmartSoC & work on next-gen designs. ๐ฉ careers@smartsocs.com. #HiringNow #DesignVerification #SV #UVM #PCIE #Ethernet #SmartSoC #VLSICareers #ChipDesign
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How was @DAC 2024 in San Francisco? You can see for yourself, through the eyes of our colleagues who flew there. โ๏ธThey came back with conference insights and marvelous videos of the cityscape to share ๐ #AMIQEDA #AMIQ #designverification #semiconductors #DAC #sanfrancisco
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Do you find yourself copying and pasting chunks of Verilog/SystemVerilog code and wishing that you had created a new function or task? . Our DVT IDE can do this at the click of a button: #Verilog #SystemVerilog #CodeRefactoring #DVTIDE #DesignVerification
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Rapidus and Siemens partner to co-develop a 2nm design kit using Calibreยฎ for advanced verification and manufacturing optimization. #2nm #Calibre #designverification
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Engineers busy in the lab, exploring a custom test method involving Durability Design Verification Tests. #Pharma #DrugDevice #MedTech #Innovation #Testing #FailureAnalysis #Healthcare #DesignVerification #DurabilityTesting #FDA #UDI
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REGISTER: #verification #fpga #fpgadesign #amd #xilinx #designverification #circuitdesign #pcbdesign
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SmartSoC Solutions is hiring for multiple positions in #FormalVerification and #DesignVerification with #SV & #UVM expertise. #WalkInDrive: 05 August 2023, 10:00 AM โ 5:00 PM, Bangalore. Experienced candidates (3+ years) can apply. #SmartSoC #Interviews #WalkInDrive #Hiring
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๐์ผ๊ฐ์ด์ ์ ์ด์ ์ ์์ผ๋ฅผ ๊ฐ์ ํ๊ธฐ ์ํด์๋ ์ฐ์ํ #IC #DesignVerification ์๋ฃจ์
์ด ํ์ํ๋ฐ์. ์คํ ๋ฆฌ ์ผ๋ ํธ๋ฆญ์ ์ฐจ์ธ๋ ๊ณ ํด์๋ ์๋์ฐจ ์กฐ๋ช
์๋ฃจ์
๊ฐ๋ฐ์ ์ํด ์ง๋ฉ์ค Questa Advanced Verification ํ๋ซํผ์ ์ฑํํ์ต๋๋ค! ๐ฃ์์ธํ ์์์ ํ์ธํด๋ณด์ธ์:
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๐ Join SmartSoC's Innovation Journey! ๐ Design Verification Expert Opportunity!. ๐ Looking for PCIe, Ethernet, DDR experts with 6-12 yrs exp. in SV and UVM. ๐ Locations: Bangalore, Hyderabad. Apply: careers@smartsocs.com ๐๐ผ #SmartSoC #TechCareers #DesignVerification ๐๐ง
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Explore the power of Questa Formal Apps for unparalleled verification coverage and heightened design quality. Email us at marketing.india@prolim.com to learn more!. #PROLIM #Siemens #EDA #DesignVerification #QuestaFormal #Electronics #Engineering #QualityAssurance
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