Aldec, Inc.
@AldecInc
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Global #SemiEDA leader delivering patented technology since 1984. FPGA Design/Simulation, Functional Verification, Prototyping, Embedded, Emulation, Mil/Aero...
Worldwide
Joined January 2011
Hosted and presented by Doulos, the AXI-based Design & Verification webinar will be held twice on Friday, November 7 - at 11:00 CET and later at 10:00 PST – and introduce chip-buses and their importance. https://t.co/VIiGvYleKd
#ARM
#SoCFPGA
#BusArchitecture
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Webinar reminder: Boost FPGA Reliability with Advanced Linting and CDC Analysis is this Thursday (November 6). Join us for practical examples of how linting supports optimal code quality. https://t.co/VIiGvYkGUF
#AMD #Vivado #EDA #CodeQuality #Linting #FPGAdesign
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Join us on Friday, November 7 at either 11:00 CET or 10:00 PST when Doulos will be introducing chip buses and their importance, before going into the details of #AMBA #AXI3. Register here https://t.co/VIiGvYkGUF
#ARM
#SoCFPGA
#BusArchitecure
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Getting Started with #ActiveHDL in #Efinity. This application note includes a sample Verilog design provided by #Efinix. https://t.co/2aJMBBM4f3
#EfinixFPGA
#FPGA
#FPGAdesign
#FPGAsimulation
#FPGAverification
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Want to learn how hardware-in-the-loop accelerates project validation and helps identify issues earlier in the design cycle? Join us on October 16 at either 16:00 CET or 11:00 PST. https://t.co/VIiGvYleKd
#EDA
#FDPGA
#FPGADesign
#FPGASimulation
#HardwareInTheLoop
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Are you attending #FPGAworld in Stockholm, Sweden on September 9? Don’t miss our ‘End-to-End Cipher Validation Using #VUnit, TySOM, and Riviera-PRO’ presentation at 10.25. Register here https://t.co/ZAxNwiFTwM
#EDA
#FPGA
#FPGAdevelopment
#FPGASoC
#SoCFPGA
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Do you want to transition your #FPGAbased projects seamlessly from prototyping to deployment? Check out our TySOM embedded prototyping solutions here https://t.co/GD8ACwc6k4
#EDA
#TySOM
#DevelopmentBoard
#AMD
#AMDFPGA
#MicrochipFPGA
#SystemonChip
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Learn about linting and see a demonstration of how early-stage performance optimization can streamline timing closure in #Vivado. Join us this Thursday, September 4 at either 16:00 CET or 11:00 PST. https://t.co/VIiGvYleKd
#AMDFPGA
#FPGA
#CodeQuality
#EDA
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Join us this Thursday (August 21) for our Automated Regression Testing for #VHDL #Verilog webinar, during which you will learn how to convert your testbenches into fully automated, repeatable regression flows. https://t.co/VIiGvYkGUF
#EDA
#FPGA
#FPGADesign
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Join us on Thursday, August 21 at 16:00 CET or 11:00 PST and we will show you how to turn a legacy #VHDL testbench into an HDLRegression-ready testbench using a compact Python script. https://t.co/VIiGvYkGUF
#EDA #HDL #Verilog #ContinuousIntegration
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It never hurts to revisit the basics. See how Riviera-PRO addresses the verification needs of engineers crafting tomorrow's FPGA and SoC devices https://t.co/u9PKtPxAzf
#EDA #FPGA #FPGAdesign #FPGAsimulation #FPGAverification
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Riviera-PRO release 2025.04 is now available. Learn more about #Riviera-PROand to request a free evaluation license here https://t.co/FJgQMBubaX
#SystemVerilog #Verilog #VHDL #EDA #FPGA #FPGAdesign #FPGAdevelopment #FPGAsimulation #FPGAverification
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Well done all. Staff at Lycoming Engines complete a three-day #DO254practitioners’ course, delivered by Aldec. Check out our DO-254 compliance solutions here https://t.co/ji02CEc8O9.
#Aerospace #Airsafety #Aviation #EDA #SafetyCritical
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Why VUnit? For the answer, join us at 15:05 on day 2 (July 2) of FPGA Conference Europe in Munich, Germany. See the conference agenda and register here https://t.co/TKdalrQzp2.
#fpgaconference25
#VUnit
#EDA
#FPGA
#VHDL
#SystemVerilog
#HDL
fpga-conference.eu
The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, focusses on user-oriented, practically applicable solutions that developers can quickly integrate into...
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In our latest blog we discuss the benefits of integrating Azure’s cloud computing platform, the open-source #VUnit test environment and Riviera-PRO. https://t.co/ilXqHzrIvU
#EDA
#FPGA
#ContinuousIntegration
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Reminder: the second installment in our two-part #FPGA Verification with #VHDL and #UVVM webinar is this Thursday (June 19). We will be live at 16:00 CEST and 11:00 PST. Register here https://t.co/VIiGvYkGUF
#EDA
#FPGAVerification
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Our customer support portal allows you to manage support tickets, receive notifications as we respond, track progress and download fixes/solutions, and access past support cases. https://t.co/7emWCY3yQZ
#EDA
#TechSupport
#TechnicalSupport
#FPGA
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Join us on Thursday, June 19 for the second installment in our two-part #FPGA Verification with #VHDL and #UVVMwebinar. We will be live at 16:00 CEST and 11:00 PST. View the agenda and register here https://t.co/VIiGvYkGUF
#EDA
#FPGAVerification
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Join us at Space Tech Expo USA https://t.co/fpPjOxhsTH We’re on booth 126 and will be showcasing our RTAX/RTSX adaptor boards and our RTL simulation and debugging solutions. #EDA #Space #SpaceTechnology #FPGA #FPGAverification #RadHard #RadiationTolerant
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