Are you attending #FPGAworld in Stockholm, Sweden on September 9? Don’t miss our ‘End-to-End Cipher Validation Using #VUnit, TySOM, and Riviera-PRO’ presentation at 10.25. Register here #EDA.#FPGA.#FPGAdevelopment.#FPGASoC.#SoCFPGA

Do you want to transition your #FPGAbased projects seamlessly from prototyping to deployment? Check out our TySOM embedded prototyping solutions here #EDA.#TySOM.#DevelopmentBoard.#AMD.#AMDFPGA.#MicrochipFPGA.#SystemonChip

Learn about linting and see a demonstration of how early-stage performance optimization can streamline timing closure in #Vivado. Join us this Thursday, September 4 at either 16:00 CET or 11:00 PST. #AMDFPGA.#FPGA.#CodeQuality.#EDA

Join us this Thursday (August 21) for our Automated Regression Testing for #VHDL #Verilog webinar, during which you will learn how to convert your testbenches into fully automated, repeatable regression flows. #EDA.#FPGA.#FPGADesign

Join us on Thursday, August 21 at 16:00 CET or 11:00 PST and we will show you how to turn a legacy #VHDL testbench into an HDLRegression-ready testbench using a compact Python script. #EDA #HDL #Verilog #ContinuousIntegration

It never hurts to revisit the basics. See how Riviera-PRO addresses the verification needs of engineers crafting tomorrow's FPGA and SoC devices #EDA #FPGA #FPGAdesign #FPGAsimulation #FPGAverification

Riviera-PRO release 2025.04 is now available. Learn more about #Riviera-PROand to request a free evaluation license here #SystemVerilog #Verilog #VHDL #EDA #FPGA #FPGAdesign #FPGAdevelopment #FPGAsimulation #FPGAverification

Well done all. Staff at Lycoming Engines complete a three-day #DO254practitioners’ course, delivered by Aldec. Check out our DO-254 compliance solutions here #Aerospace #Airsafety #Aviation #EDA #SafetyCritical

Why VUnit? For the answer, join us at 15:05 on day 2 (July 2) of FPGA Conference Europe in Munich, Germany. See the conference agenda and register here #fpgaconference25.#VUnit.#EDA.#FPGA.#VHDL.#SystemVerilog.#HDL.

In our latest blog we discuss the benefits of integrating Azure’s cloud computing platform, the open-source #VUnit test environment and Riviera-PRO. #EDA.#FPGA.#ContinuousIntegration

Reminder: the second installment in our two-part #FPGA Verification with #VHDL and #UVVM webinar is this Thursday (June 19). We will be live at 16:00 CEST and 11:00 PST. Register here #EDA.#FPGAVerification

Our customer support portal allows you to manage support tickets, receive notifications as we respond, track progress and download fixes/solutions, and access past support cases. #EDA.#TechSupport.#TechnicalSupport.#FPGA

Join us on Thursday, June 19 for the second installment in our two-part #FPGA Verification with #VHDL and #UVVMwebinar. We will be live at 16:00 CEST and 11:00 PST. View the agenda and register here #EDA.#FPGAVerification

Join us at Space Tech Expo USA We’re on booth 126 and will be showcasing our RTAX/RTSX adaptor boards and our RTL simulation and debugging solutions. #EDA #Space #SpaceTechnology #FPGA #FPGAverification #RadHard #RadiationTolerant

Check out our latest Active-HDL tutorial video, titled ‘3rd Party Flows: Team-based Development with Tortoise Git’ here #EDA #IntelQuartus #IntelFPGA #Altera #FPGA #FPGAsimulation #FPGAverification #TortoiseGit

Our 2-part FPGA Verification with #VHDL and #UVVM webinar series starts on May 8. Register here #EDA.#FPGA.#FPGAdesign.#FPGAdevelopment.#ADMFPGA.#IntelFPGA.#LatticeFPGA.#MicrochipFPGA

Our latest Active-HDL tutorial video demonstrates the creation of a VHDL block diagram design, its conversion into VHDL code, and simulation of the design. #EDA.#FPGA.#FPGAdesign.#FPGAsimulation.#FPGAverification

ALINT-PRO provides designers with a means of identifying and fixing clock-domain crossing (CDC) issues. Check out dynamic analysis ALINT-PRO videos 6.5 and 6.6 here #Linting.#CodeQuality.#CDC.#EDA.#HDL.#HardwareDesign.#FPGA

Registration is now open for a special two-part webinar series on using the Universal #VHDL Verification Methodology (#UVVM) to verify #FPGA designs. Part 1 is on May 8, and part 2 is on June 19. #EDA.#FPGAdesign.#FPGAverification