
Andreas Olofsson
@zeroasic
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Moved to https://t.co/s8sZ4LI6W0
Cambridge, MA
Joined January 2011
Get ready for the post Moore wafer-scale era. Check out our latest paper showing RTL simulation of a million cores processor. (RISC-V)
arxiv.org
Scaling up hardware systems has become an important tactic for improving performance as Moore's law fades. Unfortunately, simulations of large hardware systems are often a design bottleneck due to...
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This post shows how to build and verify your own chip(let) in Python. Writing SV testbenches is not fun, Switchboard and SiliconCompiler improves life quality! 😉Try it out and let us know what you think.
zeroasic.com
Democratizing silicon
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We have open sourced our "Universal Memory Interface" protocol for chiplets. Includes a complete reference implementation. Spread the word.🙏
github.com
Universal Memory Interface (UMI). Contribute to zeroasiccorp/umi development by creating an account on GitHub.
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