SmartDV Technologies
@smartdv
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Don’t allow other IP suppliers to force one-size-fits-all cores into your design. Get the IP you need, tailored to your specs, with SmartDV: IP Your Way.
Bengaluru, India | San Jose CA
Joined October 2010
Great to meet up with past, current, and prospective customers at ChipEx25! We look forward to continuing our support for Israel's semiconductor community with SmartDV's best-in-class Design and Verification IPs, fully customizable to meet each customer's specific requirements.
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We’re exhibiting at ChipEx and are excited to reconnect with the chip design community in Israel. See you at the Tel Aviv Convention Center!.
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Many thanks to the CXL community and organizers for an outstanding event. It was truly inspiring to connect with peers, exchange ideas, and see the growing momentum and enthusiasm around CXL technologies. Excited to see what’s ahead! .#CXLDevCon2025
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See us at two events in May:. ChipEx 2025 | Booth C2.May 13-14 | Tel Aviv. Presentation: "Error-Redundant Implementation of Commercial IP Cores: A Practical Example".May 20 | 5:40pm CEST.FPGA Developer's Forum | Switzerland.
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Flashback to DVCon China 2025, where SmartDV AE Wuchang Wang had a great time reconnecting with existing customers and building new relationships. It was a valuable opportunity for in-depth networking and sharing insights. Excited to continue growing these partnerships!
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#CXLDevCon2025 is this week! On Wednesday at 11:30 catch SmartDV's Ettore Giliberti as he discusses “CXL UVM VIP – The Challenges of Keeping Pace with New Specification Revisions.” .
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Visit us Thursday at @designreuse IP-SoC Day Silicon Valley! Look for exhibit table #21. Make sure to catch SmartDV's Ettore Giliberti at 3:15 when he discusses "Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!"
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We will be speaking at two upcoming conferences:. “Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!”.April 24 - D&R IP-SoC Silicon Valley. “CXL UVM VIP – The Challenges of Keeping Pace with New Specification Revisions”.April 30 - CXL DevCon
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ICYMI: It’s not too late to watch Philipp Jacobsohn’s talk from D&R IP-SoC in Grenoble earlier this month! . Check out the video here:
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Philipp Jacobsohn and Sunil Kumar wrote a #whitepaper on porting #ASIC IP cores to #FPGA. If you’ve considered undertaking this sort of #engineering, the paper offers a high-level blueprint . Download the paper:
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On our diverse team of Smarties, our colleagues have many talents. For example: Ettore Giliberti was a winner of the wine tasting contest during the @designreuse IP-SoC reception in Grenoble! (Maybe it was to be expected for an Italian, who lives in Spain, visiting France! 🍷)
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A glimpse of Philipp Jacobsohn’s presentation at @designreuse IP-SoC Grenoble today! . If you’d like to watch the video of Philipp’s session, you can do so here:
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On the D&R IP-SoC program this morning in Grenoble: Philipp Jacobsohn's presentation about the trials, tribulations, and benefits (!) of porting ASIC IP cores to FPGA. You're going to learn a lot in this session! 🤓
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Coucou tout le monde à Grenoble ! 👋🏻. Miss your chance to see us yesterday? You have another chance! 😌. Follow the example of a sharp colleague from @Fraunhofer (pictured, second photo) and stop by our @designreuse IP-SoC table for an #I2C #FPGA demo with Philipp & Ettore! 💻
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If you're at the @designreuse IP-SoC Conference in Grenoble this week, say hi to our team! Ettore Giliberti and Philipp Jacobsohn will be there. Stop by our exhibit table to see an FPGA demo, and don't miss Philipp's presentation on Wednesday about porting ASIC IP cores to FPGA.
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Driving success together: we’re delighted to help RANiX equip the next generation of smart vehicles! . #SDIO #V2X #vehicletoeverything #automotive #ISO26262 #ASILB #ADAS #safety #smartvehicle
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