We have posted an article "GEMM based on the RISC-V Vector Extension (Part 3)" which evaluated a GEMM-compatible floating-point matrix multiplication performance.

We have posted an article "GEMM based on the RISC-V Vector Extension (Part 2)" which evaluated vector load/store performance.

Chipyard 1.9.0 has been released.

We have posted an article "Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 2)" which introduces the OpenCL support of Vortex, a RISC-V based open source GPGPU.

In "Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference", researchers extend Ara, a RISC-V vector processor.

GCC-12.2 doesn't seem to support RISC-V Vector intrinsic.

We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.

The ELEN of RISC-V Vector extension in QEMU 7.2 defaults to 64 and supports in the range [8, 64].

We ran rvv-vlen-tests to test VLEN of the Vector extension on QEMU 7.2 for RISC-V. The VLEN value in QEMU 7.2 defaults to 128 and supports in the range [128, 1024].

We ran riscv-hyp-tests to test specific features of the Hypervisor extension on QEMU 7.2 for RISC-V.

The QEMU 7.0 ChangeLog has the following description of the Vector extension for RISC-V. - Add support for ratified 1.0 Vector extension.- Support for the Zve64f and Zve32f extensions.- Drop support for draft 0.7.1 Vector extension.

We are testing OpenPiton + Ariane (now known as CVA6) on the Nexys Video FPGA board.

We ran simple tests of the Bit Manipulation extensions (Zb[a|b|c|s]) and the Scalar Cryptography extensions (Zbk*, Zkn*) on QEMU 7.2 for RISC-V.

The QEMU 7.1 ChangeLog has the following description of the Scalar Cryptography extensions for RISC-V. - Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions.

The QEMU 6.2 ChangeLog has the following description of the Bit Manipulation extension for RISC-V. - Add Zb[abcs] instruction support.- Remove RVB support.

The QEMU 7.0 ChangeLog has the following description of the Hypervisor extension for RISC-V. - Mark Hypervisor extension as non experimental.- Enable Hypervisor extension by default.

The repository that added the RISC-V Hypervisor extension to CVA6 is below.

In "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration", researchers add the RISC-V Hypervisor extension to CVA6.

We made OpenBLAS compatible with 32-bit RISC-V and evaluated the performance of GEMM (GEneral Matrix-to-matrix Multiply) on the Nexys Video FPGA board with octa-core VexRiscv SoC.

We ran simple tests of Bit Manipulation extensions (Zb[a|b|c|s]) and Scalar Cryptography extensions (Zbk*, Zkn*) on RISC-V SoC with Rocket Chip and LiteX. #RISCV #RocketChip #LiteX