Good news, the PDK generation tool finally spits out standard cells which look as if they could be working when being built with a given DRC. We'll see with the next test wafer. https://t.co/cHnHs9MlO8

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Its Alive: first Vgs-Id characteristics of a PMOS transistor (L10/W10) measured: Vth is approx. 0.6V, quadratic behavior clearly seen.

A little bit of variation in the over etching of the oxide below the polysilicon, but etching the thicker poly gates (250nm~300nm) worked fine. Next: junction implants, spacers and silicide. Lets see whether the leakage now is gone with this batch.

Little update: @leviathanch has had the flu this week and has just now recovered. The NMOS/PMOS switch at +/- 950mv as dimensioned after thermal compensation (still rampup budget left). We still have some 100kOhm shorts between D/G/S but this will be fixed on the next sample.

Here a polysilicon Zener diode, measured in forward bias direction.

Ok. Here: The first measurement results from a switching, truely _Libre_ PMOS transistor.

Here's the silicon island with a 2.5 micron deep trench filled with LTO. The angle doesn't exceed 45 degrees and the height between oxide and silicon is below 100nm. CMP-ing is a nice thing. As soon as I've got access to Cirie200 I'll etch the nickel interconnets.

The silicide on top of the polysilicon has such a low resistance, that it's being rounded down to zero ohm. That's the gate material! Those gates will have an insanely high cutoff frequency!

So we now did the nitride spacers and the silicide and under the microscope we can nicely see, that we don't have shortcircuits anymore. Unfortunately, we can only to the interconnect Mo/Tue because we're not allowed in the lab Sa/Sun... :-(

Today: Before and after the dry etching of a 20nm silicon nitride film. This shadow on the around the structure after dry etching is our nitride spacer. Lets hope it's enough for keeping it from shorting again with the junctions during silicidation... Wish us luck tomorrow!

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The first evaluation of TiSi2 contact and Aluminum interconnect. Measurement data follows.

On Monday, we're going to strip the resist from the polysilicon gates and then perform the nimplant step after applying and exposing the 6400 resist. Then we RTA it for a few minutes, sputter titanium and RTP it again. That should give us transistors around Wednesday.

Cleaning the unreacted Titanium with RCA-1 turned out to be more complicated than expected. Also the Ammonia smell is terrible. We're now redoing the this experiment, but will clean it with H2SO4:H2O2 instead. Pictures of the new results will follow on Monday or Tuesday.

Today we successfully got the formation of a 77nm thick TiSi2 layer working. It's so thin, that it's hardly visible, but the multi meter beeped, so it's conducting. Tomorrow we'll provide pictures of our test dummy poly gates with a 77nm TiSi2 film. Stay tuned!

For the last two weeks we've been fighting with the formation of thin film silicide on mono crystalline silicon. Today we've got a recipe working. It just was a bad idea trying to remove uncreacted Titanium with HF, turns out TiSi2 dissloved in HF😅 Tomorrow again, with RCA...

In case you've ever been wondering how thermally stable C54 TiSi polycide looks like. It's royal blue, and it has a very very low ohmic resistance.

Now we've got STI together with LTO and CMP, we etch the FOX tomorrow. Wish us luck that we've got better results this time!

And the oxide openings for sputtering the metal interconnect into. Second attempt with TMAH instead of dry etching until we can evaluate DRY-only and put both measurements into our ALF file ranges.