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InstLatX64

@InstLatX64

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x86/x64, SIMD, #AVX512, "Aha!" moments. I have been writing code since 1986.

Budapest, Europe
Joined August 2014
Don't wanna be here? Send us removal request.
@InstLatX64
InstLatX64
9 months
My future posts will be published there first, and here only later
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@InstLatX64
InstLatX64
8 hours
There are a few working #PantherLake B0_2 among #Intel test machines: (CPUID C06C2, 12c/12t (4P+4E+4LPE probably), 3.0 GHz base freq, no HTT & #AVX512, Intel 18A).#CougarCove #Darkmont.For comparison, #LunarLake was 3100MHz (8c/8t 4P+4LPE) at similar stage
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@InstLatX64
InstLatX64
6 months
Trace of a working A0 #PantherLake (3/3.2GHz, CPUID C06C0, #Intel 18A process) in coreboot project:.
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@InstLatX64
InstLatX64
1 day
First(?) official mention of #AMD #Sorano (the expected #EPYC 8005 #SP6 socket #Zen5-based #Siena follower):.page 25
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@InstLatX64
InstLatX64
11 months
New #AMD #Zen5 entries:.- #StrixPoint2 B30F00 [1].- #StrixPoint3 B30F80 [1].- #Weisshorn B50F00 added [1].- #Sorano, #Breithorn, #BreithornD codenames [1], [2].Sources:.[1]:[2]:Commit:.
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@InstLatX64
InstLatX64
1 day
RT @TDevilfish: @InstLatX64 It's the 2.5D D2D interface. Used in stxH and yes pretty much everything z6.
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@InstLatX64
InstLatX64
3 days
#GMI vs #SSBDCI difference at the physical layer (if I understand correctly): 16 vs 2x32 wires. Has anyone measured the #StrixHalo Core2core bandwidth?.Sources:.[1]:[2]:
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@InstLatX64
InstLatX64
3 days
What does this abbreviation #SSBDCI mean? Will the #AMD #Zen6 also use this?.
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@InstLatX64
InstLatX64
3 days
What does this abbreviation #SSBDCI mean? Will the #AMD #Zen6 also use this?.
@InstLatX64
InstLatX64
3 days
#AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 70h, Revision A0 Processors" v3.00 57930 pdf #Zen5 #StrixHalo CPUID B70F00."High Bandwidth Chiplet IO: #SSBDCI"
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@InstLatX64
InstLatX64
3 days
#AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 70h, Revision A0 Processors" v3.00 57930 pdf #Zen5 #StrixHalo CPUID B70F00."High Bandwidth Chiplet IO: #SSBDCI"
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@InstLatX64
InstLatX64
10 months
#AMD released the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 44h, Revision B0 Processors" v3.00 57896 pdf (#Zen5 #GraniteRidge CPUID B40F40).
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@InstLatX64
InstLatX64
4 days
New histogram results, this time leaving the unified code path. #AMD-specific code finally reaches 4 bytes/clk. Hand-optimized asm, of course.
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@InstLatX64
InstLatX64
5 months
Always there is a faster code: My current byte-#histogram results vs 2024 .It is interesting, that how closer is #Intel #GoldenCove to the theoretical limit (0.343 <-> 0.372) than #AMD #Zen5 (0.207 <-> 2.54).#GFNI
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@InstLatX64
InstLatX64
4 days
First on the blue side, of course.
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@InstLatX64
InstLatX64
4 days
I expected more competition in HW-news. #Sorano + #AMD logo.#Intel #Pantherlake bootlog.#GMI vs #SSBDCI.#SP5 vs #SP7.etc. Are they all boring?.
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@InstLatX64
InstLatX64
7 days
Will #AMD #Zen6 support the #AVX10 versioning? Will AMD support CPUID.24h (or the AMD-equivalent) what required for the single query?.cc: @LeslieB82382206, @philparkbot.
@HtooMyatLin3
Htoo Myat Lin
13 days
@InstLatX64 Will amd also benefit from this?.
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@InstLatX64
InstLatX64
7 days
#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 7.0:.APX_NCI_NDD_NF = CPUID.(EAX=0x29,ECX=0x00):EBX[0]
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@InstLatX64
InstLatX64
7 months
#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 6.0:.#AMX_MOVRS #AMX_TRANSPOSE #MSR_IMM
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@InstLatX64
InstLatX64
12 days
RT @InstLatX64: @bajorgensen It seems so, #AVX10_2 (and probably #APX) will be universally supported on #Intel CPUs, just #AMX remains #Xeo….
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@InstLatX64
InstLatX64
12 days
[1]: [2]: 2/2.
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@InstLatX64
InstLatX64
12 days
New #Intel CPUIDs [1]:.- #NovaLake 300F10 (Fam18 mod1).- #NovaLakeL 300F30 (Fam18 mod3).New dump:.-Core Ultra 9 275HX C0662 #ArrowLakeHX.New #AMD #Zen6 #Venice #EPYC socket assignments [2]:.-B50F00, BC0F00 #SP7 16 mc.-B90F00, BA0F00 #SP8 8 mc.GitHub:.1/2
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@InstLatX64
InstLatX64
27 days
New CPUIDs:.- #AMD #KrackanPoint2 CPUID B60F80 [1].- #Intel #BartlettLake CPUID B06F6 [2].[1]: [2]: GitHub:.Krackan2 official source:.
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@InstLatX64
InstLatX64
13 days
Finally an explicit mention of 512b #AVX10_2 for future #Intel desktop CPUs ( #NovaLake, of course):.
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@InstLatX64
InstLatX64
14 days
A cool list of #Intel projects with CPUIDs and SKUs:.
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@InstLatX64
InstLatX64
17 days
#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 3 General-Purpose and System Instructions" 24594 to v3.37.#AVX512 #PREFETCHI.
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@InstLatX64
InstLatX64
1 year
#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 3 General-Purpose and System Instructions" 24594 pdf to v3.36 with #RMPREAD instruction:.
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@InstLatX64
InstLatX64
17 days
#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 2" 24593 pdf to v3.43 with #AVX512.
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@InstLatX64
InstLatX64
1 year
#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 2" 24593 pdf to v3.41 with #MOESDIF protocol, Instruction-Based Sampling Virtualization, Performance Monitoring Counter Virtualization, etc.
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@InstLatX64
InstLatX64
19 days
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@InstLatX64
InstLatX64
2 months
#Intel refreshed the #AVX10_2 specification to 5.0:.VDPPHPS is not #AVX10_VNNI_INT, it's much more logical
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