The first cohort of the UKESF Semiconductor Skills Development Course is LIVE and running at full capacity!. Proud to support this UK Gov-funded programme alongside @theUKESF, building next-gen skills in #semiconductors, #FPGA & #digitaldesign. 👉

We're exhibiting at #MicroelectronicsUK 2025 - the UK’s flagship microelectronics event, live at ExCeL London this September!. Don’t miss our very own Dr David Long on: “Digital Verification for FPGA & ASIC Designers”. Read more here -

Join millions who have switched to Grok.

Doulos KnowHow Webinar: Understanding Random Stability in SystemVerilog and UVM. 📅August 20th. ⏰Europe & Asia: 10am (BST) & Americas: 10am (PDT). Find out more & register: Webinar partners: @Cadence .Presenter: Matthew Taylor. #DoulosTraining

Rust for Embedded Systems course starts Aug 18!. Learn to apply Rust in real-world embedded dev: toolchain setup, memory mgmt, C/C++ integration, concurrency & more. Includes hands-on labs + VM + Doulos materials. 👉 #EmbeddedRust #Rust.

Join our FREE online workshop with @AMD on Versal™ Adaptive SoCs! . Learn how to unlock AI Engine power, optimize with SIMD datapaths, and explore C++ APIs. 🚀. 📅 Aug 28-29. 🔗 Register now: #EmbeddedAI #AIEngines #Versal #AMD #DoulosTraining

Updated! - Essential Edge AI for Embedded Developers course has been refreshed. Gain hands-on skills in MLOps, model training, transfer learning, TinyML, object detection & more – all focused on real-world edge deployment. Find out more: #EdgeAI.

First webinar this August: Working With Devicetrees 📅 August 8th 📷#DoulosTraining #Toradex #NXP #EmbeddedLinux #EmbeddedSystems

Doulos is proud to be sponsoring the Open Source Summit 2025, hosted in Amsterdam!. We’ll be there presenting “Zephyr Workqueues: How They Work and Queue” on Monday, August 25 at 11:20 CEST. Read more here: #ZephyrRTOS #OSSummit #OpenSource

Friday’s webinar - Getting Started with SystemVerilog Randomization.It will introduce the key concepts of randomization & constraints, including language constructs, the generation & constraint of data & randomization features and configuration approaches.

We are delighted to add SystemVerilog for New Designers to the Doulos self-paced training portfolio!. This course is designed to help you gain the essential skills for FPGA and ASIC design. Find out more below!. #doulostraining #systemverilog

RT @ZephyrIoT: What’s really happening inside your Zephyr workqueues? This hands-on talk at #ZephyrDevSummit shows you:.✔️Scheduling & meta….

This Wednesday’s webinar - Understanding MPSoC Real-Time Processing.Explore the Arm® powered real-time processing capability of the UltraScale+ MPSoC and the hardware and software requirements for implementing time sensitive applications. Register:

Next week's online workshop: Migrating to the AMD Vitis Embedded Software Development IDE .📅July 24 & 25.This workshop examines the tools and techniques required for software design and development using the Vitis unified software platform. Register:

In this Doulos KnowHow tip, Doulos Senior Member Technical Staff, Simon Goda explains exactly what an SBOM actually is and what data it should contain. Watch now: #DoulosTraining #Linux #Embeddedsystems #doulosondemand

This Friday’s webinar - Introduction to Android Automotive.📅July 18.⏰Europe & Asia: 10am (BST) & Americas: 10am (PDT).This webinar provides a valuable insight into the Android Automotive OS that runs "In Vehicle Infotainment" systems. Find out more:

Tomorrow’s webinar - Clock Domain Crossing.📅July 16.⏰Europe & Asia: 10am (BST) & Americas: 10am (PDT).This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

🎉The Doulos team had a fantastic time at Christchurch Quay for our summer party!. From boat trips to mini golf, it was a day full of sunshine, laughter, and great memories. A special highlight was celebrating Kelvin Bampfield’s incredible milestone – 25 years at Doulos!

In this Doulos KnowHow tip, VHDL Guru Doug Perry (author of "VHDL: Programming by Example") explains common mistakes from those new to VHDL when using VHDL statements. #DoulosTraining #Doulosondemand #VHDL

Migrating to the AMD Vitis Embedded Software Development IDE Online Workshop.📅July 24 & 25 ⏰Available worldwide.This workshop examines the tools and techniques required for software design and development using the Vitis unified software platform.

This newly updated course covers features added by Modern C++ standards (C++11, C++14 and C++17) along with an overview of C++20 and C++23 for embedded microcontrollers. #doulostraining #embeddedsystems