As part of @sochubfi, CPC successfully taped out a customized TTA-based Digital Signal Processor (DSP). "Beaivi DSP" was fully designed and C-programmed by using the OpenASIP tools developed by the group since the 2000s: @ITC_TampereUni.

Link to the full playlist:

Blazing-fast image creation – using just your voice. Try Grok Imagine.

The results of past 3 years of hard work on the edge AI offloading SW stack based on PoCL-R were shown in the AISA Y3 demo day last Friday. Feature showcase videos available (spoiler: Crazyflie can edge offload AI!): @vga_tuni @OpenCLorg @Bitcraze_se.

OpenASIP v2.1 released: It adds support for LLVM 17, speeds up DSE thanks to a more intelligent LLVM BE generation, and more! @sochubfi.

RT @HepolaKari: Our article introduces a dual-mode processor that utilizes ILP statically when available, without suffering from low code d….

Maarten Molendijk from @TUeindhoven presented "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC" in @ieee_iccd. BrainTTA was designed and programmed using the tools. @sochubfi.

RT @portablecl: PoCL-R is a new backend for offloading OpenCL tasks to other nodes on the network. Now with OpenCL API offloading can be pe….

HW accelerators require vendor-specific steps to use. A generic memory-mapped interface helps integrating them to a diverse OpenCL platform. Our interfacing work is now published in and the code available in the @portablecl repo! @openclapi @CPSoSAWARE.

Check a demo made with some of our final technical outcomes from the @CPSoSAWARE EU project: Nano-PoCL, PoCL-R and AlmaIF v2. Offloading OpenVX from a nanodrone to an FPGA using OpenCL as the offload API. Exciting stuff! @openclapi @portablecl.

OpenASIP 2.0 is out! It has the first #RISCV customization features, improved FU generation, LLVM 15, IP wrapping, among other new features! @sochubfi @CPSoSAWARE @openhwgroup

RT @HepolaKari: VLIW processors exploit ILP efficiently but suffer from bad code density in serial parts where instruction packets cannot b….

RT @HepolaKari: The open-standard RISC-V ISA has made the open source hardware community more active but there has been a lack of tools for….

OpenASIP 1.25 is now out. It supports LLVM 14 and adds partial retargetable inline asm support and loop buffer compilation features. Thanks to @CPSoSAWARE for supporting the @CustomParComp. group's contributions! @sochubfi @llvmorg.

RT @JoonasMultanen: Emerging memory technologies could enable extremely energy-efficient compute devices in the future. Read how domain wal….

OpenASIP 1.24 released! Adds LLVM 13 and first steps for Blocks CGRA support. Thanks @FitOptiVis. @CPSoSAWARE @sochubfi for supporting the @CustomParComp group's contributions!.

A presentation about our ongoing work on PoCL-R: Distributed OpenCL Runtime for Low Latency Offloading available: @portablecl @openclapi @FitOptiVis @CPSoSAWARE.

CPC is looking forward to contributing to this interesting joint project in its distributed high performance low latency computing aspects!.

OpenASIP 1.23 released! It's mainly a maintenance release that adds LLVM 12 support and removes support for older than LLVM 11 to clean up the code base. Thanks @FitOptiVis @CPSoSAWARE @sochubfi .for supporting the @CustomParComp group's work!.