Aller hop hop hop, on vote 😁

Merci @NicoMartinFC de me donner l'opportunité de faire découvrir @RickandMorty aux membres de ma famille qui, je les comprends, sont plus réceptifs à tes émissions qu'à mes plaidoyers ! 😁😁😁

I was surprised to see people's head up in the bus until I realized #whatsapp #facebook and #instagram are #down. Come on, let's just make everyday like this 15 minutes bus ride. #disconnect

Hello, world. My first look at my forever home. #CountdownToMars

#GDRSOC2IMC Q2: en recherche #IMC etes vous plutot team #RRAM, team #SRAM , autre #flash #dram, un mix de toutes?

Today's @hipeac tutorial on how to use #gem5 to explore architectures got really popular with more than 50 morning-attendees and talks from @iremboybat @sergiabadal @marinazapater @AlexLevisse. @IBMResearch @la_UPC @eslepfl @Wiplash_Eu @hes_so #IMC #wireless #HIPEAC21 #riscv

I am excited to give a talk during this tutorial in #HIPEAC21. With @marinazapater, @sergiabadal, and @iremboybat we will discuss how #gem5 can be used to optimize heterogeneous architectures. @hipeac @eslepfl @hes_so @la_UPC @IBMResearch @Wiplash_Eu #riscv #wireless #IMC

(5/5) You can check out the paper here : https://t.co/PwGcoLRyau and the presentation there : https://t.co/1oIA5YnGNt via @YouTube @eslepfl #AI #EdgeComputing

(4/5) We identified the same kind of trade trade-offs in our BLADE architecture, in which, when accelerating convolutional layers with #InMemoryComputing, there is an optimal array size to maximize energy/performance gains. The *good* size. related tweet: https://t.co/vrpj2K4QqR

(3/5) It is really interesting to realize that, what you need is not "a bit of RRAM", or "a lot of RRAM". But rather a finely tuned memory size adapted to your application target.

(2/5) We called it SHyCache and it is a hybrid cache hardware architecture with a supporting programming model, like those that enable GP-GPU acceleration. As in a CNN +/-40% of the read accesses are for weights, deterministically allocating these variables to RRAM makes sense.

(1/5) Back in 2014 when starting my Ph.D., I wondered how these RRAM techs, I was working on, could make sense in a complete system. We just got published a really nice work on how to manage hybrid RRAM/SRAM caches with a complete HW/SW stack. Exciting trade-offs there!

Do majority-vote mechanisms help with controlling irrational behaviors? seems to work better in computers though.

Last Friday, the WiPLASH consortium held a plenary telco to kickstart the semester after the summer break. Progress is steady, and we hope to share soon advances in #graphene #antennas, chip-scale interconnects, accelerator-driven architectures, etc... Stay tuned!

Our paper just got published on @ComputerSociety Transactions on VLSI. Collaborating with @imec_int on the effects of BTI CMOS aging in real #edge systems running real applications! @eslepfl @David__Atienza https://t.co/NO6NJM40CA

We just received the Best Paper Award from @isvlsi2020 . On the use of integrated #DCDC converters with flowcell array #LiquidCooling technology in #HPC #3D #MPSoC. @eslepfl Link to the work: https://t.co/VLgrUimujO

Discover the BLADE, the accomplishment of 2.5years of work in @eslepfl published in @IEEEorg Transactions on Computers. IMC simulated from circuit to real Edge AI applications. @ComputerSociety #AI #inMemoryComputing https://t.co/NUkicxllYh

Checkout out our @eslepfl recently published article with @univamu and @CEA_Leti on new RRAM programming schemes and their effects on Edge systems running AI workloads. #openaccess #RRAM #AI @IEEEAccess https://t.co/54tt82t41k

Prof. David Atienza is interviewed by @FrontiersIn about the ongoing development of #coughvid: https://t.co/nUAYhB4W5s

An online, fruitful, and thrilling 2nd plenary meeting with the @Wiplash_Eu team! On our way to break boundaries and explore on-chip #wireless #AI systems enabled by #graphene antennas and #InMemoryComputing.