Adele HARS Profile
Adele HARS

@AdeleHars

Followers
501
Following
2K
Media
272
Statuses
6K

Writing about technology and giving it context. Former Editor-in-Chief of SOI News.

Joined December 2010
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@AdeleHars
Adele HARS
4 years
I’ve got a new hat as a contributor to the @OJOYOSHIDA Report. Subscribe & read on! @junkoyoshida @Bolaji_Ojo_Tech.
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@AdeleHars
Adele HARS
4 years
“The Ojo-Yoshida Report Explores the Unintended Consequences of Technology Innovation” - and I am excited to be part of this mission!.
@junkoyoshida
Junko Yoshida
4 years
Our mission is to strike a balance between covering the industry’s stated intentions and exploring all consequences, both promised and unexpected.
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@AdeleHars
Adele HARS
5 years
The SOI ecosys is buzzing w/activity. Latest #chipdesign updates in SOI News (just emailed: read here!) #FDSOI #RFSOI #edgeAI #edgecomputing #AIoT #IoT #wearables #5G #mmWave #photonics @verisilicon @Thalia_IP_Reuse @CEA_Leti @Soitec_EN @soiconsortium
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@AdeleHars
Adele HARS
5 years
RT @soiconsortium: Read our latest post: Solving a Problem like Reuse – an FD-SOI #Analog IP Perspective from Thalia .
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@AdeleHars
Adele HARS
5 years
RT @FollowASN: Heads up! Advanced Substrate News has a new name: SOI News. We'll keep posting to this Twitter feed, but be sure to also fol….
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@AdeleHars
Adele HARS
5 years
RT @designreuse: New IP: 10-bit, 2 GSPS ADC in @ST_World 28nm #FDSOI from Alphacore from #semIP.
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@AdeleHars
Adele HARS
5 years
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@AdeleHars
Adele HARS
5 years
RT @soiconsortium: @NXP Be there! @soiconsortium members @NXP & @Arm will demo RT1060 crossover MCU (in member @Sam….
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@AdeleHars
Adele HARS
5 years
RT @rom_lem: Learn more about our #SamurAI chip: a low-power #IoT node with an energy-efficient #MachineLearning accelerator! #FDSOI #RISCV….
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@AdeleHars
Adele HARS
5 years
RT @OpenSky_PR: @CEA_Leti achieves key milestone on the path to high-performance #3D #monolithic #CMOS integration .
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@AdeleHars
Adele HARS
5 years
Hey #chipdesign folks: do you really have to design4worstcase? NO!! You leave too much on the table. W/#FDSOI #bodybias you design for typical & tune post-silicon. Don't bin. Win big. @verisilicon CEO explains. #EdgeComputing #AIoT #IoT #wearables #edgeAI
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@AdeleHars
Adele HARS
5 years
So, what about #FDSOI #analog IP for #chipdesign folks? Port or start from scratch? @Thalia_IP_Reuse CTO says there's a 3rd option. Read his perspective here. #AIoT #IoT #EdgeComputing #edgeAI @soiconsortium @GLOBALFOUNDRIES @SamsungSemiUS #Automotive.
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@AdeleHars
Adele HARS
5 years
RT @COBO_Group: When will silicon photonics supplant copper interfaces for VLSI and beyond for datatcom? @soiconsortium @SEMICONWest https:….
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@AdeleHars
Adele HARS
5 years
RT @FollowASN: Our latest post: Solving a Problem like Reuse – an FD-SOI Analog IP Perspective from Thalia @Thalia_….
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@AdeleHars
Adele HARS
5 years
RT @DolphinDesignFR: Discover our computing platforms:.RAPTOR - #NeuralNetworkAccelerator.PANTHER - #DSPCluster.Choose the performance. htt….
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@AdeleHars
Adele HARS
5 years
RT @soiconsortium: More & more analog designers are reaping the benefits of #FDSOI. At Thalia we’ve been at the forefront of some of these….
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@AdeleHars
Adele HARS
5 years
RT @GLOBALFOUNDRIES: From @eetimes: "As the revival of U.S. chip manufacturing gathers momentum . SkyWater Technology and GlobalFoundries….
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eetimes.com
SkyWater Technologies and GlobalFoundries will jointly produce chips for the military while looking to scale beyond.
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@AdeleHars
Adele HARS
5 years
More #lowpower #FDSOI #chipdesign making headlines for @latticesemi @SamsungUS.
@latticesemi
Lattice Semiconductor
5 years
Introducing Lattice #Certus-NX, the new low power, general purpose #FPGA and the second device developed on the Lattice Nexus Platform. Lattice Certus-NX delivers up to twice the I/O density per mm2 in comparison to similar competing FPGAs. Learn more:
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@AdeleHars
Adele HARS
5 years
RT @soiconsortium: Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of….
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